公开(公告)号：US09091487B2

公开(公告)日：2015-07-28

申请号：US13152184

申请日：2011-06-02

申请人： Sang Chul Byon ,  Yong Ho Kim ,  Dae Keun Park ,  Nam Joon Lee

发明人： Sang Chul Byon ,  Yong Ho Kim ,  Dae Keun Park ,  Nam Joon Lee

IPC分类号： F28D7/14 ,  F28D7/10 ,  F28F1/42 ,  B21D53/06

CPC分类号： B21D53/06 ,  F28D7/106 ,  F28D7/14 ,  F28F1/426 ,  F28F2001/428 ,  F28F2210/06 ,  F28F2265/28 ,  Y10T29/49361 ,  Y10T29/49377 ,  Y10T29/49391

摘要： A double pipe type heat exchanger includes an inner pipe having a first flow path defined therein and an outer pipe arranged around the inner pipe to define a second flow path between the inner pipe and the outer pipe. The inner pipe includes a spiral groove formed on an outer circumferential surface of the inner pipe to extend along a longitudinal direction of the inner pipe. The outer pipe includes a reduced diameter portion protruding inwardly so that the inner surface of the outer pipe is intermittently contacted with the outer circumferential surface of the inner pipe.

摘要翻译： 双管式热交换器包括具有限定在其中的第一流路的内管和围绕内管布置的外管，以在内管和外管之间限定第二流动路径。 内管包括形成在内管的外周面上的螺旋槽，沿着内管的长度方向延伸。 外管包括向内突出的减小直径部分，使得外管的内表面与内管的外周表面间歇地接触。

公开(公告)号：US07534720B2

公开(公告)日：2009-05-19

申请号：US11608500

申请日：2006-12-08

申请人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

发明人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835

摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

摘要翻译： 制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。 蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。 通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。 并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。 去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。 并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

公开(公告)号：US20070082484A1

公开(公告)日：2007-04-12

申请号：US11608500

申请日：2006-12-08

申请人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

发明人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835

摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

摘要翻译： 制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。 蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。 通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。 并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。 去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。 并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

公开(公告)号：US20050054192A1

公开(公告)日：2005-03-10

申请号：US10910922

申请日：2004-08-04

申请人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

发明人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

IPC分类号： H01L21/28 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835

摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

摘要翻译： 制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。 蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。 通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。 并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。 去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。 并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

公开(公告)号：US20120280245A1

公开(公告)日：2012-11-08

申请号：US13364189

申请日：2012-02-01

申请人： Chuan Cheah ,  Dae Keun Park

发明人： Chuan Cheah ,  Dae Keun Park

IPC分类号： H01L29/778 ,  H01L21/56

CPC分类号： H03K17/74 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/01 ,  H01L25/18 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15747 ,  H01L2924/181 ,  H03K17/567 ,  H03K17/687 ,  H03K2017/6875 ,  H01L2924/00

摘要： Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

摘要翻译： 已经公开了具有冲压引线框架的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括III族氮化物晶体管，其具有堆叠在III族氮化物晶体管的源极之上的二极管的阳极，以及冲压引线框架，包括耦合到III族氮化物晶体管的栅极的第一弯曲引线和 二极管和耦合到III族氮化物晶体管的漏极的第二弯曲引线。 弯曲的引线暴露可表面安装的各个平坦部分。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以一次组装多个封装，与需要单独封装处理和外部来源部件的常规方法相比，可以实现高集成度和成本节省。

公开(公告)号：US08853707B2

公开(公告)日：2014-10-07

申请号：US13364219

申请日：2012-02-01

申请人： Chuan Cheah ,  Dae Keun Park

发明人： Chuan Cheah ,  Dae Keun Park

IPC分类号： H01L23/34 ,  H01L23/433 ,  H01L23/495 ,  H03K17/74 ,  H01L23/00 ,  H03K17/567 ,  H03K17/687 ,  H01L25/18

CPC分类号： H03K17/687 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/01 ,  H01L24/37 ,  H01L24/40 ,  H01L25/18 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/181 ,  H03K17/567 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

摘要翻译： 已经公开了具有蚀刻引线框架的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括具有堆叠在III族氮化物晶体管的源极上的二极管的阳极的III族氮化物晶体管，以及被蚀刻以形成耦合到III族氮化物晶体管的栅极的第一引线框桨形部分的引线框架，以及 二极管的阳极和耦合到III族氮化物晶体管的漏极的第二引线框桨形部分。 引导框桨形部分使封装能够可表面安装。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以一次组装多个封装，与需要单独封装处理和外部来源部件的常规方法相比，可以实现高集成度和成本节省。

公开(公告)号：US08546849B2

公开(公告)日：2013-10-01

申请号：US13364242

申请日：2012-02-01

申请人： Chuan Cheah ,  Dae Keun Park

发明人： Chuan Cheah ,  Dae Keun Park

IPC分类号： H01L29/778 ,  H01L29/20

CPC分类号： H01L23/49844 ,  H01L21/56 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L25/074 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/06181 ,  H01L2224/32145 ,  H01L2224/37147 ,  H01L2224/40145 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15787 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00

摘要： Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

摘要翻译： 已经公开了利用封装支撑表面上的夹子的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括附接到封装支撑表面并具有堆叠在III族氮化物晶体管的源极上的二极管的阳极的III族氮化物晶体管，耦合到III族氮化物晶体管的栅极的第一导电夹和阳极 并且耦合到III族氮化物晶体管的漏极的第二导电夹。 导电夹子连接到封装支撑表面并暴露出可表面安装的相应的平坦部分。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以将低成本印刷电路板（PCB）用于封装支撑表面，因此可以避免昂贵的无引线制造工艺以实现成本有效的制造。

公开(公告)号：US08368194B1

公开(公告)日：2013-02-05

申请号：US13487713

申请日：2012-06-04

申请人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

发明人： Robert Francis Darveaux ,  Michael Barrow ,  Miguel Angel Jimarez ,  Jae Dong Kim ,  Dae Keun Park ,  Ki Wook Lee ,  Ju Hoon Yoon

IPC分类号： H01L23/29

CPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105

摘要： An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

摘要翻译： 曝光的芯片包覆成型的倒装芯片封装包括衬底。 芯片安装在基板的上表面上。 该包装还包括填充模具的活性表面和基材的上表面之间的空间的模具盖。 模具帽包括主表面，从基板的上表面延伸到主表面的侧壁，与模具的非活性表面共面并从模具的非活性表面的外围边缘向外延伸的环形表面，并且突出 表面在主表面和环形表面之间延伸。 模具盖不覆盖模具的非活性表面，使得从模具到周围环境的热传递最大化并且封装厚度最小化。

公开(公告)号：US20120280247A1

公开(公告)日：2012-11-08

申请号：US13364242

申请日：2012-02-01

申请人： Chuan Cheah ,  Dae Keun Park

发明人： Chuan Cheah ,  Dae Keun Park

IPC分类号： H01L29/20 ,  H01L21/56

CPC分类号： H01L23/49844 ,  H01L21/56 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L25/074 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/06181 ,  H01L2224/32145 ,  H01L2224/37147 ,  H01L2224/40145 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2224/92246 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/15787 ,  H03K17/567 ,  H03K17/687 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/84 ,  H01L2224/83 ,  H01L2924/00

摘要： Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

摘要翻译： 已经公开了利用封装支撑表面上的夹子的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括附接到封装支撑表面并具有堆叠在III族氮化物晶体管的源极上的二极管的阳极的III族氮化物晶体管，耦合到III族氮化物晶体管的栅极的第一导电夹和阳极 并且耦合到III族氮化物晶体管的漏极的第二导电夹。 导电夹子连接到封装支撑表面并暴露出可表面安装的相应的平坦部分。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以将低成本印刷电路板（PCB）用于封装支撑表面，因此可以避免昂贵的无引线制造工艺以实现成本有效的制造。

公开(公告)号：US20120280246A1

公开(公告)日：2012-11-08

申请号：US13364219

申请日：2012-02-01

申请人： Chuan Cheah ,  Dae Keun Park

发明人： Chuan Cheah ,  Dae Keun Park

IPC分类号： H01L23/34 ,  H01L21/60 ,  H01L27/06

CPC分类号： H03K17/687 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/01 ,  H01L24/37 ,  H01L24/40 ,  H01L25/18 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/181 ,  H03K17/567 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

摘要翻译： 已经公开了具有蚀刻引线框架的高压级联III族氮化物半导体封装的一些示例性实施例。 一个示例性实施例包括具有堆叠在III族氮化物晶体管的源极上的二极管的阳极的III族氮化物晶体管，以及被蚀刻以形成耦合到III族氮化物晶体管的栅极的第一引线框桨形部分的引线框架，以及 二极管的阳极和耦合到III族氮化物晶体管的漏极的第二引线框桨形部分。 引导框桨形部分使封装能够可表面安装。 以这种方式，与传统的导线接合封装相比，可以实现减小的封装占地面积，改进的浪涌电流能力和更高的性能。 此外，由于可以一次组装多个封装，与需要单独封装处理和外部来源部件的常规方法相比，可以实现高集成度和成本节省。