公开(公告)号：US20120217563A1

公开(公告)日：2012-08-30

申请号：US13465649

申请日：2012-05-07

申请人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin

发明人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻通过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

公开(公告)号：US08183619B1

公开(公告)日：2012-05-22

申请号：US09539458

申请日：2000-03-30

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

公开(公告)号：US07116174B2

公开(公告)日：2006-10-03

申请号：US10953897

申请日：2004-09-29

申请人： Hao Fang ,  Cameron Carroll Rabe

发明人： Hao Fang ,  Cameron Carroll Rabe

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： H03F1/302 ,  H03F2200/453

摘要： A method and apparatus for compensating a base current of a bipolar junction transistor by replicating operating conditions of the BJT in a compensating circuit. An output current of the compensating circuit is fractionally related to the base current and thus can be supplied to an operational circuit comprising the BJT to compensate the base current. In a preferred embodiment, the BJT is operated between BVCEO and BVCBO and the base current to be compensated flows from the BJT.

摘要翻译： 一种用于通过在补偿电路中复制BJT的工作条件来补偿双极结型晶体管的基极电流的方法和装置。 补偿电路的输出电流与基极电流分数有关，因此可以提供给包括BJT的运算电路以补偿基极电流。 在优选实施例中，BJT在BVCEO和BVCBO之间运行，待补偿的基极电流从BJT流出。

公开(公告)号：US20060134881A1

公开(公告)日：2006-06-22

申请号：US11013415

申请日：2004-12-17

申请人： Been-Jon Woo ,  Hao Fang ,  Mon-Chin Tsai

发明人： Been-Jon Woo ,  Hao Fang ,  Mon-Chin Tsai

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method of forming a trench isolation device capable of reducing corner recess comprising forming a pad oxide layer and a silicon nitride mask layer on a semiconductor base, and forming a trench by etching. Next, a liner oxide layer is formed on the semiconductor base and on the surface of the shallow trench. Then, the silicon nitride mask layer will be etched to reveal the corner. Finally, a layer of oxide is formed on the base to fill up the trench so that the trench isolation device can be completed. The present invention is designed to solve the corner recess problem, reduce generation of kick effect, and enhance the device characteristics and electrical quality.

摘要翻译： 一种形成能够减少角凹部的沟槽隔离装置的方法，包括在半导体基底上形成衬垫氧化物层和氮化硅掩模层，并通过蚀刻形成沟槽。 接下来，在半导体基底和浅沟槽的表面上形成衬垫氧化物层。 然后，将蚀刻氮化硅掩模层以露出拐角。 最后，在基底上形成一层氧化物以填充沟槽，从而可以完成沟槽隔离装置。 本发明旨在解决拐角凹陷问题，减少踢球效应的产生，提高装置特性和电气质量。

公开(公告)号：US20060066408A1

公开(公告)日：2006-03-30

申请号：US10953897

申请日：2004-09-29

申请人： Hao Fang ,  Cameron Rabe

发明人： Hao Fang ,  Cameron Rabe

IPC分类号： H03F3/04

CPC分类号： H03F1/302 ,  H03F2200/453

摘要： A method and apparatus for compensating a base current of a bipolar junction transistor by replicating operating conditions of the BJT in a compensating circuit. An output current of the compensating circuit is fractionally related to the base current and thus can be supplied to an operational circuit comprising the BJT to compensate the base current. In a preferred embodiment, the BJT is operated between BVCEO and BVCBO and the base current to be compensated flows from the BJT.

公开(公告)号：US06610580B1

公开(公告)日：2003-08-26

申请号：US09563179

申请日：2000-05-02

申请人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

发明人： Maria C. Chan ,  Hao Fang ,  Mark S. Chang ,  Mike Templeton

IPC分类号： H01L2176

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/11517

摘要： In a first aspect of the present invention, a flash memory array is disclosed. The flash memory array comprises a substrate comprising active regions, wherein the active regions are defined by a layer of nitride, the layer of nitride including a top surface. The flash memory array further comprises shallow trenches in the substrate, each of the shallow trenches including a layer of oxide, the layer of oxide having a top surface, wherein the top surface of the layer of oxide and the top surface of the layer of nitride are on substantially the same plane and channel areas wherein the occurrences of polyl stringers in the channel areas is substantially reduced. In a second aspect of the present invention, a method and system for fabricating a flash memory array is disclosed. The method comprises the steps of providing a layer of nitride over a substrate, forming trenches in the substrate and then growing a layer of oxide in the trenches. Finally, the layer of oxide is polished back. Through the use of the preferred embodiment of the present invention, a shallow trench isolation process is implemented as opposed to LOCOS process, thereby reducing the occurrence of polyl stringers in the channel area. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent regions is substantially reduced.

摘要翻译： 在本发明的第一方面，公开了一种闪存阵列。 闪存阵列包括包含有源区的衬底，其中有源区由氮化物层限定，氮化物层包括顶表面。 闪存阵列还包括衬底中的浅沟槽，每个浅沟槽包括一层氧化物，氧化层具有顶表面，其中氧化层的顶表面和氮化层的顶表面 在基本相同的平面和通道区域上，其中通道区域中多边形桁条的出现被大大减少。 在本发明的第二方面中，公开了一种用于制造闪存阵列的方法和系统。 该方法包括以下步骤：在衬底上提供氮化物层，在衬底中形成沟槽，然后在沟槽中生长一层氧化物。 最后，氧化层被抛光。 通过使用本发明的优选实施例，与LOCOS工艺相反，实现了浅沟槽隔离工艺，从而减少了通道区域中多边形的发生。 因此，相邻区域之间不需要的电短路径的发生显着减少。

公开(公告)号：US06372577B1

公开(公告)日：2002-04-16

申请号：US09443647

申请日：1999-11-18

申请人： Hao Fang

发明人： Hao Fang

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

摘要： A method of forming a NAND-type flash memory device (200 ) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.

摘要翻译： 一种形成NAND型闪速存储器件（200）的方法包括：在芯区（305）中形成用于一个或多个闪存单元的层叠栅极闪速存储器结构（346），并形成具有第一栅极氧化物 336）和用于芯区（305）中的选择栅极晶体管（344）和外围区域（328）中的低电压晶体管（342）的栅极导体（338）。 另外，NAND型闪速存储器件（200）包括一个包含层叠栅极快闪存储器单元结构（346）和选择栅极晶体管（344）的核心区域（305）和包括一个 低压晶体管（342）和高压晶体管（350），其中选择栅晶体管（344）和低压晶体管（342）的结构基本相同。

公开(公告)号：US06300658B1

公开(公告)日：2001-10-09

申请号：US09368073

申请日：1999-08-03

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

公开(公告)号：US06235586B1

公开(公告)日：2001-05-22

申请号：US09352801

申请日：1999-07-13

申请人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

发明人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524

摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极 区; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的所述第一氧化物层的至少一部分上生长第二氧化物层; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂的非晶硅层，所述第一原位掺杂的非晶硅层具有从约至在的厚度; 在第一原位掺杂的非晶硅层的至少一部分上沉积介电层; 在所述电介质层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成快闪存储器单元，以及在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层， 和第二掺杂非晶硅层，选择栅晶体管包括第一氧化物层，第二氧化物层，第一原位掺杂非晶硅层，介电层和第二掺杂非晶硅层。

公开(公告)号：US06177322B1

公开(公告)日：2001-01-23

申请号：US09177817

申请日：1998-10-23

申请人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L29/1033 ,  H01L29/41775

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

摘要翻译： 形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入 代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。