公开(公告)号：US06177322B1

公开(公告)日：2001-01-23

申请号：US09177817

申请日：1998-10-23

申请人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L29/1033 ,  H01L29/41775

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

摘要翻译： 形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入 代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。

公开(公告)号：US5844840A

公开(公告)日：1998-12-01

申请号：US914543

申请日：1997-08-19

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

IPC分类号： G11C8/08 ,  G11C16/06

CPC分类号： G11C8/08

摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.

摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

公开(公告)号：US5909396A

公开(公告)日：1999-06-01

申请号：US127991

申请日：1998-08-03

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

IPC分类号： G11C8/08 ,  G11C16/06

CPC分类号： G11C8/08

摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.

摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管的阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

公开(公告)号：US07076703B1

公开(公告)日：2006-07-11

申请号：US10305700

申请日：2002-11-26

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C29/00

CPC分类号： G11C29/804

摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

摘要翻译： 一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个 一组相邻列，包括有缺陷的列。 所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。 冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。 所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。 通常，有缺陷的列的每一侧将有多个列。

公开(公告)号：US07038950B1

公开(公告)日：2006-05-02

申请号：US10982296

申请日：2004-11-05

申请人： Darlene Hamilton ,  Ed Hsia ,  Pau-Ling Chen

发明人： Darlene Hamilton ,  Ed Hsia ,  Pau-Ling Chen

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C2211/5621

摘要： Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensated program verify level from that of the NEW data to improve memory reliability and insure minimal uniform stress levels to the array. The improved programming algorithm prevents older data from being needlessly refreshed, thus mitigating stress to the cells that eventually causes the data areas to decay at different rates and become prematurely unreliable.

摘要翻译： 提供将新数据编程到一组存储器单元的未编程位中的方法。 该方法应用一种交互式编程算法，可以对新数据，参考（REF）数据和现有或OLD数据进行单独验证和编程。 OLD数据被分别验证为与NEW数据的补偿程序验证级别，以提高内存可靠性并确保阵列的最小均匀应力水平。 改进的编程算法防止老化的数据被不必要地刷新，从而减轻细胞的压力，最终导致数据区域以不同的速率衰减并变得过早地不可靠。

公开(公告)号：US06622201B1

公开(公告)日：2003-09-16

申请号：US09525078

申请日：2000-03-14

申请人： Michael VanBuskirk ,  Pau-Ling Chen

发明人： Michael VanBuskirk ,  Pau-Ling Chen

IPC分类号： G06F1200

CPC分类号： G11C7/22

摘要： A sequential access memory structure includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus. Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections. Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus. The sections of memory elements in the array comprise half-pages. The storage comprises two sections, each of which has a half-page of memory elements, and the carry output produces the carry signal prior to reading data from a last half-page of the array out of the storage onto the output bus. Data from the last half-page is read onto the output bus while data from a first half-page of an array of a next downstream memory is being loaded into its storage.

摘要翻译： 顺序访问存储器结构包括输出总线和多个顺序存取存储器，每个存取存储器连接到输出总线。 每个存储器包括具有多个可顺序读取的存储器元件的存储器阵列，当阵列的读取已基本完成时用于产生进位信号的进位输出，以及用于响应于进位信号而引起阵列读取的进位输入。 每个存储器的进位输出分别以链排列连接到另一个下游存储器的进位输入，并且进位信号使得阵列被顺序读取到输出总线上。 每个存储器还包括连接在阵列和输出总线之间的读写存储器，存储器包括多个部分。 来自阵列的数据被加载到存储的一部分中，同时从存储器的另一部分读取数据到输出总线上。 阵列中的内存元素部分包括半页。 存储器包括两个部分，每个部分具有半页存储器元件，并且进位输出在从阵列的最后半页从存储器中读取数据到输出总线之前产生进位信号。 来自上一个半页的数据被读取到输出总线上，而来自下一个下游存储器阵列的前半页的数据被加载到其存储器中。

公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06373742B1

公开(公告)日：2002-04-16

申请号：US09689036

申请日：2000-10-12

申请人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Shane C. Hollmer ,  Pau-Ling Chen

IPC分类号： G11C506

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C5/063

摘要： A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

摘要翻译： 一种用于从存储器阵列的两侧进行解码的解码器。 解码器位于存储器阵列的两侧。 解码器包括从存储器阵列连接到路由线路的驱动器电路。 为了减小解码器的大小，一些路由线从存储器阵列的一侧延伸，并且剩余的路由线从存储器阵列的另一侧延伸。

公开(公告)号：US06288951B1

公开(公告)日：2001-09-11

申请号：US09675940

申请日：2000-09-29

申请人： Pau-Ling Chen ,  Binh Quang Le

发明人： Pau-Ling Chen ,  Binh Quang Le

IPC分类号： G11C700

CPC分类号： G11C5/145

摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.

摘要翻译： 一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。

公开(公告)号：US06262469B1

公开(公告)日：2001-07-17

申请号：US09047237

申请日：1998-03-25

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer

IPC分类号： H01L2900

CPC分类号： H01L29/94 ,  H01L27/0811 ,  H01L29/66189

摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.

摘要翻译： 电容器分压器包括两个电容器，它们串联在两个电压源之间。 第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。 电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。