公开(公告)号：US20050054268A1

公开(公告)日：2005-03-10

申请号：US10966744

申请日：2004-10-14

申请人： Rodney Kistler ,  David Hemker ,  Yehiel Gotkis ,  Aleksander Owczarz ,  Bruno Morel ,  Damon Williams

发明人： Rodney Kistler ,  David Hemker ,  Yehiel Gotkis ,  Aleksander Owczarz ,  Bruno Morel ,  Damon Williams

IPC分类号： B24B37/005 ,  B24B49/02 ,  B24B49/10 ,  B24B49/14 ,  H01L21/304 ,  H01L21/66 ,  G06F19/00

CPC分类号： B24B37/005 ,  B24B49/10 ,  B24B49/14

摘要： In chemical mechanical polishing, a wafer carrier plate is provided with a cavity for reception of a sensor positioned very close to a wafer to be polished. Energy resulting from contact between a polishing pad and an exposed surface of the wafer is transmitted only a very short distance to the sensor and is sensed by the sensor, providing data as to the nature of properties of the exposed surface of the wafer, and of transitions of those properties. Correlation methods provide graphs relating sensed energy to the surface properties, and to the transitions. The correlation graphs provide process status data for process control.

公开(公告)号：US06749491B1

公开(公告)日：2004-06-15

申请号：US10033501

申请日：2001-12-26

申请人： Yehiel Gotkis ,  David Wei ,  Aleksander Owzarz

发明人： Yehiel Gotkis ,  David Wei ,  Aleksander Owzarz

IPC分类号： B24B2120

CPC分类号： B24B37/04 ,  B24B21/04 ,  B24B21/20

摘要： An apparatus for reducing non-uniform stretch of a belt used in the CMP system is disclosed. The belt that may be used with the apparatus extends between a first roller and a second roller to define a belt loop with an inner surface and an outer surface to be used for CMP. The apparatus includes a compensating roller that has a first end and a second end where the first end and second end extends a width of the belt. The first end and the second end have a first diameter. The center of the roller has a second diameter that is less than the first diameter. The compensating roller has a symmetrically tapered shape that extends between each of the first end and second end to the center. The compensating roller is positioned inside of the belt loop, and is applied to the inner surface of the belt loop to reduce non-uniform stretch of the belt.

公开(公告)号：US06719874B1

公开(公告)日：2004-04-13

申请号：US09823800

申请日：2001-03-30

申请人： Yehiel Gotkis ,  Aleksander A. Owczarz ,  Miguel A. Saldana ,  David Wei ,  Damon Vincent Williams

发明人： Yehiel Gotkis ,  Aleksander A. Owczarz ,  Miguel A. Saldana ,  David Wei ,  Damon Vincent Williams

IPC分类号： B24B100

CPC分类号： B24B37/32

摘要： A chemical mechanical planarization (CMP) system having a polishing pad, a carrier body for holding a wafer, a retaining ring, and an active retaining ring support is provided. The active retaining ring is defined by a circular ring having a thickness and a width. The circular ring is defined by an elastomeric material. The circular ring is configured to be placed between the retaining ring and the carrier body. The circular ring has a plurality of voids therein, and the plurality of voids are defined in locations around the circular ring. The circular ring has a compressibility level that is set by the elastomeric material and the plurality of voids.

摘要翻译： 提供了具有抛光垫，用于保持晶片的载体主体，保持环和主动挡环支架的化学机械平面化（CMP）系统。 主动保持环由具有厚度和宽度的圆形环限定。 圆环由弹性体材料限定。 圆环被配置成放置在保持环和载体之间。 圆环中具有多个空隙，并且多个空隙限定在圆环周围的位置。 圆环具有由弹性体材料和多个空隙设定的可压缩水平。

公开(公告)号：US06653224B1

公开(公告)日：2003-11-25

申请号：US10032480

申请日：2001-12-27

申请人： Yehiel Gotkis ,  Rodney Kistler ,  Leonid Romm ,  Te Hua Lin

发明人： Yehiel Gotkis ,  Rodney Kistler ,  Leonid Romm ,  Te Hua Lin

IPC分类号： H01L214763

CPC分类号： H01L21/3212 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684

摘要： Methods for fabricating semiconductor structures having LowK dielectric properties are provided. In one example, a copper dual damascene structure is fabricated in a LowK dielectric insulator including forming a capping film over the insulator before features are defined therein. After the copper is formed in the features, the copper overburden is removed using ultra-gentle CMP, and then the barrier is removed using a dry etch process. Following barrier removal, a second etch is performed to thin the capping film. The thinning is configured to reduce the thickness of the capping film without removal, and thereby reducing the K-value of the LowK dielectric structure.

摘要翻译： 提供了制造具有LowK介电特性的半导体结构的方法。 在一个示例中，铜双镶嵌结构制造在LowK电介质绝缘体中，包括在其上限定特征之前在绝缘体上形成覆盖膜。 在特征中形成铜之后，使用超柔和的CMP去除铜覆盖层，然后使用干蚀刻工艺去除阻挡层。 在去除屏障之后，进行第二次蚀刻以使封盖膜变薄。 该薄化被配置为在不去除的情况下减小封盖膜的厚度，从而降低LowK电介质结构的K值。

公开(公告)号：US06585572B1

公开(公告)日：2003-07-01

申请号：US09644135

申请日：2000-08-22

申请人： Miguel A. Saldana ,  John M. Boyd ,  Yehiel Gotkis ,  Aleksander A. Owczarz

发明人： Miguel A. Saldana ,  John M. Boyd ,  Yehiel Gotkis ,  Aleksander A. Owczarz

IPC分类号： B24B100

CPC分类号： B24B37/20 ,  B24B53/017 ,  H01L21/30625

摘要： A chemical mechanical polishing (CMP) system is provided. A carrier has a top surface and a bottom region. The top surface of the carrier is designed to hold and rotate a wafer having a one or more formed layers to be prepared. A preparation head is also included and is designed to be applied to at least a portion of the wafer that is less than an entire portion of the surface of the wafer. Preferably, the preparation head and the carrier are configured to rotate in opposite directions. In addition, the preparation head is further configured to oscillate while linearly moving from one of the direction of a center of the wafer to an edge of the wafer and from the edge of the wafer to the center of the wafer so as to facilitate precision controlled removal of material from the formed layers of the wafer.

摘要翻译： 提供化学机械抛光（CMP）系统。 载体具有顶表面和底部区域。 载体的顶表面被设计成保持和旋转具有一个或多个待制备的成形层的晶片。 还包括制备头，并且被设计成被施加到小于晶片表面的整个部分的晶片的至少一部分。 优选地，制备头和载体被构造成沿相反方向旋转。 此外，准备头还被配置为在从晶片的中心的方向之一到晶片的边缘并且从晶片的边缘到晶片的中心线性移动的同时振荡，以便于精确控制 从晶片的成形层去除材料。

公开(公告)号：US06340326B1

公开(公告)日：2002-01-22

申请号：US09493978

申请日：2000-01-28

申请人： Rod Kistler ,  Yehiel Gotkis

发明人： Rod Kistler ,  Yehiel Gotkis

IPC分类号： B23B2900

CPC分类号： B24B53/017 ,  B24B37/26 ,  B24B49/04 ,  B24B51/00

摘要： A system and method for polishing semiconductor wafers includes a rotatable polishing pad movably positionable in a plurality of partially overlapping configurations with respect to a semiconductor wafer. A pad dressing assembly positioned coplanar, and adjacent, to the wafer provides in-situ pad conditioning to a portion of the polishing pad not in contact with the wafer. The method includes the step of radially moving the polishing pad with respect to the wafer.

摘要翻译： 用于抛光半导体晶片的系统和方法包括可移动的抛光垫，其可相对于半导体晶片以多个部分重叠的构造定位。 与晶片共面并相邻设置的衬垫修整组件为不与晶片接触的抛光垫的一部分提供原位衬垫调节。 该方法包括相对于晶片径向移动抛光垫的步骤。

公开(公告)号：US07755061B2

公开(公告)日：2010-07-13

申请号：US11983069

申请日：2007-11-07

申请人： Luca Grella ,  Leonid Baranov ,  Yehiel Gotkis

发明人： Luca Grella ,  Leonid Baranov ,  Yehiel Gotkis

IPC分类号： G21K1/02

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/0435 ,  H01J2237/0453

摘要： One embodiment relates to a dynamic pattern generator for reflection electron beam lithography which includes conductive pixel pads, an insulative border surrounding each conductive pixel pad so as to electrically isolate the conductive pixel pads from each other, and conductive elements coupled to the conductive pixel pads for controllably applying voltages to the conductive pixel pads. The conductive pixel pads are advantageously cup shaped with a bottom portion, a sidewall portion, and an open cavity. Another embodiment relates to a pattern generating apparatus which includes a well structure with sidewalls and a cavity configured above each conductive pixel pad. The sidewalls may include alternating layers of conductive and insulative materials. Other embodiments, aspects and feature are also disclosed.

摘要翻译： 一个实施例涉及用于反射电子束光刻的动态图案发生器，其包括导电像素焊盘，围绕每个导电像素焊盘的绝缘，以将导电像素焊盘彼此电隔离，以及耦合到导电像素焊盘的导电元件， 可控地向导电像素焊盘施加电压。 导电像素焊盘有利地为杯形，其具有底部，侧壁部分和开放空腔。 另一个实施例涉及一种图案生成装置，其包括具有侧壁的阱结构和在每个导电像素垫之上配置的空腔。 侧壁可以包括交替的导电和绝缘材料层。 还公开了其它实施例，方面和特征。

公开(公告)号：US07528349B1

公开(公告)日：2009-05-05

申请号：US11532748

申请日：2006-09-18

申请人： Yehiel Gotkis ,  Arik Donde ,  Vincenzo Lordi

发明人： Yehiel Gotkis ,  Arik Donde ,  Vincenzo Lordi

IPC分类号： H05B3/68 ,  F26B19/00

CPC分类号： H01L21/67103 ,  G03F7/70716 ,  G03F7/70875 ,  H01L21/67109

摘要： A temperature stabilization system, method, composition of matter and substrate processing system are disclosed. A heat absorbing material is disposed in thermal contact with a substrate. The heat absorbing material is characterized by a solid-liquid phase transition temperature that is in a desired temperature range for material processing the substrate. When the substrate is subjected to material processing that results in heat transfer into or out of the substrate the solid-liquid phase transition of the heat absorbing material stabilizes the temperature of the substrate.

摘要翻译： 公开了温度稳定系统，方法，物质组成和衬底处理系统。 吸热材料与衬底热接触地设置。 吸热材料的特征在于固液相转变温度在用于材料加工基材的期望温度范围内。 当基板经受导致热传递到基板中的材料加工时，吸热材料的固 - 液相变使基板的温度稳定。

公开(公告)号：US20090010526A1

公开(公告)日：2009-01-08

申请号：US11622793

申请日：2007-01-12

申请人： Yehiel Gotkis ,  Sergey Lopatin ,  Mehran Nasser-Ghodsi

发明人： Yehiel Gotkis ,  Sergey Lopatin ,  Mehran Nasser-Ghodsi

IPC分类号： G06K9/00 ,  G01R31/26 ,  H01L23/58

CPC分类号： H01L22/12 ,  H01L22/34

摘要： A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.

摘要翻译： 本发明的第一实施例涉及一种用于评估集成电路晶片上的结构质量的方法。 在集成的或在测试晶片上形成的测试结构暴露于电子束和电子束激活的化学蚀刻。 电子束活化的蚀刻气体或蒸气蚀刻测试结构，其在蚀刻后分析以确定测试结构的质量的度量。 可以在统计过程控制中使用质量测量来调整用于在集成电路晶片上形成器件结构的参数。 测试结构形成在具有两个或更多个管芯的集成电路晶片上。 每个管芯具有一个或多个集成电路结构。 测试结构形成在两个或更多相邻模具之间的划线上。 每个测试结构可以在尺寸和/或组成上与一个或多个集成电路结构相对应。

公开(公告)号：US20070160107A1

公开(公告)日：2007-07-12

申请号：US11713233

申请日：2007-02-28

申请人： Yehiel Gotkis ,  Mikhail Korolik

发明人： Yehiel Gotkis ,  Mikhail Korolik

IPC分类号： G01K19/00 ,  G01N25/00 ,  G01J5/00

CPC分类号： G01B21/085

摘要： A method for measuring a metal film thickness is provided. The method initiates with heating a region of interest of a metal film with a defined amount of heat energy. Then, a temperature of the metal film is measured. Next, a thickness of the metal film is calculated based upon the temperature and the defined amount of heat energy. A chemical mechanical planarization system capable of detecting a thin metal film through the detection of heat transfer dynamics is also provided.