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    PNEUMATIC TIRE
    41.
    发明申请
    PNEUMATIC TIRE 审中-公开
    气动轮胎

    公开(公告)号：US20120097305A1

    公开(公告)日：2012-04-26

    申请号：US13266704

    申请日：2010-04-28

    申请人： Kazuya Kuroshi ,  Kenji Toyoda

    发明人： Kazuya Kuroshi ,  Kenji Toyoda

    IPC分类号： B60C13/02

    CPC分类号： B60C13/02

    摘要： A pneumatic tire (10) is provided with turbulence generating projections (100) extending in a tire radial direction and arranged in the tire side portion (30) located between the tread (20) and beads. If the length of each turbulence generating projection (100) in the radial direction of the tire is L, the Young's modulus of the material which forms the turbulence generating projection (100) is E, and the second moment of area of a cross section of the turbulence generating projection (100) taken perpendicularly to the extending direction of the projection is I, the turbulence generating projections (100) satisfy the relationship of L2≦3.5×E×I. The configuration assures the effect of heat dissipation of the tire side portion and minimizes deformation of the turbulence generating projections caused by oil flying from the outside.

    摘要翻译： 充气轮胎（10）设置有沿轮胎径向延伸的湍流产生突起（100），并且布置在位于胎面（20）和胎圈之间的轮胎侧部（30）中。 如果每个湍流产生突起（100）在轮胎径向方向上的长度为L，则形成湍流产生突起（100）的材料的杨氏模量为E，横截面积的第二矩 垂直于突起的延伸方向的湍流产生用突起（100）为I，湍流产生用突起（100）满足L2＆nlE; 3.5×E×I的关系。 该构造确保了轮胎侧部的散热效果，并且使得由从外部飞出的油引起的湍流产生突起的变形最小化。

    Organic FET having improved electrode interfaces and a fabrication method therefor
    44.
    发明授权
    Organic FET having improved electrode interfaces and a fabrication method therefor 有权
    具有改善的电极界面的有机FET及其制造方法

    公开(公告)号：US07476894B2

    公开(公告)日：2009-01-13

    申请号：US11939098

    申请日：2007-11-13

    申请人： Kenji Toyoda

    发明人： Kenji Toyoda

    IPC分类号： H01L29/08 ,  H01L35/24 ,  H01L51/00

    CPC分类号： H01L51/105 ,  H01L51/0545 ,  H01L51/0558

    摘要： An organic FET in which the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode are improved by employing a technique to increase ON-state current (driving current) and to reduce contact resistance. The organic FET includes a substrate; a gate insulating film disposed on the substrate; a metal source electrode and a metal drain electrode disposed on the gate insulating film in such a manner that they face each other in a horizontal direction; and an organic semiconductor layer covering the gate insulating film, the source electrode and the drain electrode, wherein a first organic molecule layer and a second organic molecule layer are formed on the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode.

    摘要翻译： 通过采用增加导通状态电流（驱动电流）和降低接触电阻的技术来改善其中半导体层和源极之间以及半导体层和漏极之间的界面（电极界面）的有机FET。 有机FET包括基板; 设置在所述基板上的栅极绝缘膜; 设置在栅极绝缘膜上的金属源电极和金属漏电极，使得它们在水平方向上彼此面对; 以及覆盖所述栅极绝缘膜，所述源极电极和所述漏极电极的有机半导体层，其中在所述半导体层和源极之间的界面（电极界面）上形成有第一有机分子层和第二有机分子层，以及介于 半导体层和漏电极。

    ORGANIC FET HAVING IMPROVED ELECTRODE INTERFACES AND A FABRICATION METHOD THEREFOR
    45.
    发明申请
    ORGANIC FET HAVING IMPROVED ELECTRODE INTERFACES AND A FABRICATION METHOD THEREFOR 有权
    具有改进的电极接口的有机FET及其制造方法

    公开(公告)号：US20080061290A1

    公开(公告)日：2008-03-13

    申请号：US11939098

    申请日：2007-11-13

    申请人： Kenji Toyoda

    发明人： Kenji Toyoda

    IPC分类号： H01L29/08

    CPC分类号： H01L51/105 ,  H01L51/0545 ,  H01L51/0558

    摘要： The present invention relates to an organic FET in which the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode are improved by employing a novel technique to increase ON-state current (driving current) and to reduce contact resistance. The present invention provides an organic FET having: a substrate; a gate insulating film disposed on the substrate; a metal source electrode and a metal drain electrode disposed on the gate insulating film in such a manner that they face each other in a horizontal direction; and an organic semiconductor layer covering the gate insulating film, the source electrode and the drain electrode, wherein a first organic molecule layer and a second organic molecule layer are formed on the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode.

    摘要翻译： 本发明涉及一种有机FET，其中半导体层和源电极之间以及半导体层和漏电极之间的界面（电极界面）通过采用新的技术来提高导通状态电流（驱动电流）而得到改善， 并降低接触电阻。 本发明提供一种有机FET，其具有：基板; 设置在所述基板上的栅极绝缘膜; 设置在栅极绝缘膜上的金属源电极和金属漏电极，使得它们在水平方向上彼此面对; 以及覆盖所述栅极绝缘膜，所述源极电极和所述漏极电极的有机半导体层，其中在所述半导体层和源极之间的界面（电极界面）上形成有第一有机分子层和第二有机分子层，以及介于 半导体层和漏电极。

    Nonvolatile flip-flop circuit and method of driving the same
    46.
    发明申请
    Nonvolatile flip-flop circuit and method of driving the same 有权
    非易失性触发电路及其驱动方法

    公开(公告)号：US20050206421A1

    公开(公告)日：2005-09-22

    申请号：US11080454

    申请日：2005-03-16

    申请人： Takashi Nishikawa ,  Kenji Toyoda ,  Takashi Ohtsuka

    发明人： Takashi Nishikawa ,  Kenji Toyoda ,  Takashi Ohtsuka

    IPC分类号： G11C11/22 ,  H03K3/356 ,  H03K3/289

    CPC分类号： H03K3/356008 ,  G11C11/22

    摘要： The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor (601) when the data signal D is input while a first clocked inverter (604), a second clocked inverter (603), and a third switching element (602) are turned on and a first switching element (605), a second switching element (607), and a third clocked inverter (608) are turned off; and a data output step of outputting an output signal Q (−Q) based on the held data signal D placing the first clocked inverter (604), the second clocked inverter (603), and the third switching element (602) in the OFF state and placing the first switching element (605), the second switching element (607), and the third clocked inverter (608) in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor (601).

    摘要翻译： 本发明提供了一种驱动非易失性触发电路的方法，包括以下步骤：数据保持步骤，当数据信号D（D）被利用时，利用铁电栅极晶体管（601）的铁电材料的极化来保持输入数据信号D 在第一时钟反相器（604），第二时钟反相器（603）和第三开关元件（602）导通时，第一开关元件（605），第二开关元件（607）和第三开关元件 时钟反相器（608）关闭; 以及数据输出步骤，基于将第一时钟反相器（604），第二时钟反相器（603）和第三开关元件（602）放置在OFF中的保持数据信号D输出输出信号Q（-Q） 状态，并且将第一开关元件（605），第二开关元件（607）和第三时钟反相器（608）置于导通状态，以便中断数据信号的输入并保持铁电材料的极化状态 的铁电栅极晶体管（601）。

    Image processing apparatus and method
    47.
    发明申请
    Image processing apparatus and method 审中-公开
    图像处理装置及方法

    公开(公告)号：US20050190277A1

    公开(公告)日：2005-09-01

    申请号：US11118430

    申请日：2005-05-02

    申请人： Masahiro Juen ,  Kenji Toyoda ,  Osamu Ikeda ,  Hisato Ide

    发明人： Masahiro Juen ,  Kenji Toyoda ,  Osamu Ikeda ,  Hisato Ide

    IPC分类号： G06F3/14 ,  G06F3/041 ,  G06F3/048 ,  G06T1/00 ,  G09G5/00 ,  G09G5/08 ,  H04N1/00 ,  H04N5/225 ,  H04N5/232 ,  H04N5/765 ,  H04N5/781 ,  G03C5/00

    CPC分类号： G06F3/033 ,  G06F3/04845 ,  G06T1/00 ,  H04N1/00352 ,  H04N1/00397 ,  H04N1/00411 ,  H04N2101/00

    摘要： An image processing apparatus provided with a display unit for displaying an operation picture, showing control indicia (e.g., icons) corresponding to multiple image processing functions, is operated to display the operation picture on an external display device. The operator selects one of the indicia shown on the external display device by operating an input device, such as touch screen of the apparatus or a remote control, to indicate the position of the desired one of the indicia. The operator can thereby quickly and reliably select an image processing function to be executed, without any need to view an operation picture on the display unit when making the selection.

    摘要翻译： 操作具有用于显示操作画面的显示单元的图像处理设备，显示与多个图像处理功能对应的控制标记（例如，图标），以在外部显示设备上显示操作画面。 操作者通过操作诸如设备的触摸屏或遥控器的输入设备来指示所需的一个标记的位置来选择外部显示设备上所示的一个标记。 因此，操作者能够快速，可靠地选择要执行的图像处理功能，而不需要在进行选择时在显示单元上观看操作画面。

    Ferroelectric element and a ferroelectric gate device using the same
    48.
    发明申请
    Ferroelectric element and a ferroelectric gate device using the same 有权

    公开(公告)号：US20050146917A1

    公开(公告)日：2005-07-07

    申请号：US11052794

    申请日：2005-02-09

    申请人： Kenji Toyoda ,  Takashi Ohtsuka

    发明人： Kenji Toyoda ,  Takashi Ohtsuka

    IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/866 ,  H03K17/62

    CPC分类号： G11C11/22

    摘要： A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1) comprises is applied to said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).

    Semiconductor device and learning method thereof
    49.
    发明授权
    Semiconductor device and learning method thereof 失效
    半导体器件及其学习方法

    公开(公告)号：US06844582B2

    公开(公告)日：2005-01-18

    申请号：US10434358

    申请日：2003-05-09

    申请人： Michihito Ueda ,  Kenji Toyoda ,  Takashi Ohtsuka ,  Kiyoyuki Morita

    发明人： Michihito Ueda ,  Kenji Toyoda ,  Takashi Ohtsuka ,  Kiyoyuki Morita

    IPC分类号： G06N3/063 ,  G11C27/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L45/00 ,  H01L29/76 ,  H01L27/108 ,  G06F15/18 ,  G06G7/00

    CPC分类号： H01L27/11502 ,  G06N3/0635 ,  G11C11/54 ,  G11C27/00 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11507 ,  H01L27/11521 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/1203 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/144

    摘要： A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.

    摘要翻译： 本发明的半导体器件的学习方法包括具有倍增器作为突触的神经器件，其中重量根据输入重量电压而变化，并且用作处理模拟数据的神经网络系统，其包括步骤A的步骤A 向神经装置输入预定的输入数据并计算神经装置的输出的目标值相对于输入数据与实际输出之间的误差;步骤B，通过改变神经元的重量来计算误差的变化量; 之后的乘法器，以及基于误差变化量来改变乘法器的权重的步骤C，其中在步骤B和C中，在输入用于将权重设定为基本恒定值的复位电压之后， 重量电压，通过输入与要变化的重量相对应的重量电压来改变重量。

    Heterojunction bipolar transistor and method for fabricating the same
    50.
    发明授权
    Heterojunction bipolar transistor and method for fabricating the same 失效
    异质结双极晶体管及其制造方法

    公开(公告)号：US06821870B2

    公开(公告)日：2004-11-23

    申请号：US10224468

    申请日：2002-08-21

    申请人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

    发明人： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

    IPC分类号： H01L2122

    CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/66242

    摘要： A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

    摘要翻译： 通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。 通过使Si集电体层的SiGeC基底层的晶格应变量为1.0％以下，带隙可以窄于现有实际SiGe的带隙（Ge含量为10％左右），良好 结晶可以在热处理后保持。 结果，可以实现没有实际麻烦的窄带隙基。