公开(公告)号：US06461949B1

公开(公告)日：2002-10-08

申请号：US09820305

申请日：2001-03-29

申请人： Kent Kuohua Chang ,  Chia-Hsing Chen

发明人： Kent Kuohua Chang ,  Chia-Hsing Chen

IPC分类号： H01L214763

CPC分类号： H01L27/11568 ,  H01L21/3143 ,  H01L27/115

摘要： The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.

摘要翻译： 本发明提供一种在半导体晶片中制造氮化物只读存储器（NROM）的改进栅极的方法。 首先在半导体晶片中的硅衬底的表面上分别形成底部氧化物和氮化硅层，然后在300mTorr和200-650的条件下注入五乙氧基钽（Ta（OC 2 H 5）5） 以形成作为顶部氧化物层的五氧化钽（Ta 2 O 5）层。 顶部氧化物层，氮化硅层和底部氧化物层构成氧化物 - 氧化物 - 氧化物（ONO）电介质结构。 最后，在ONO结构的表面上形成栅极导体层，以完成本发明的NROM的制造。 五氧化二钽具有高介电常数，用于降低控制栅极电压和热预算，以增加半导体晶片的耦合比和产率。

公开(公告)号：US06323047B1

公开(公告)日：2001-11-27

申请号：US09368247

申请日：1999-08-03

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L2166

CPC分类号： H01L27/11526 ,  H01L21/32137 ,  H01L22/34 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531

摘要： The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments. With the method in accordance with the present invention, a second gate over etch and its extent can be monitored without destroying the device. The method requires less time than conventional monitoring methods and is also less costly.

公开(公告)号：US06858506B2

公开(公告)日：2005-02-22

申请号：US10605122

申请日：2003-09-10

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L21/336 ,  H01L29/10

CPC分类号： H01L29/6659 ,  H01L29/1054 ,  H01L29/665

摘要： A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si1-xGex; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.

摘要翻译： 提供一种半导体器件的制造方法，其中在半导体衬底上依次形成硅锗（Si1-xGex; SiGe）层和应变硅层。 进一步在应变硅层上形成栅极氧化物层和栅极结构。 栅极结构和应变硅层分别用n型掺杂剂重掺杂以形成压缩栅极和源极/漏极区域。 在半导体衬底上进一步形成覆盖层，接着进行退火处理。 盖层随后被去除。

公开(公告)号：US06713388B2

公开(公告)日：2004-03-30

申请号：US10063199

申请日：2002-03-28

申请人： Uway Tseng ,  Ching-Yu Chang ,  Kent Kuohua Chang

发明人： Uway Tseng ,  Ching-Yu Chang ,  Kent Kuohua Chang

IPC分类号： H01L2131

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/76829 ,  H01L21/76831

摘要： A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.

摘要翻译： 存储器件形成在硅衬底上。 此后形成阻挡层以覆盖存储器件的堆叠栅极。 在阻挡层上形成吸气层，然后将吸气层平坦化至预定厚度。 然后在吸气层上形成第一阻挡层。 形成接触孔，以穿过第一阻挡层，吸气层和阻挡层，直到存储器件的表面。 之后，产生第二阻挡层以覆盖第一阻挡层和接触孔。 最后，第二阻挡层的部分被回蚀刻以在接触孔的侧壁上形成隔离隔离物。 其中，第一阻挡层和阻挡间隔物分别防止移动原子垂直扩散并横向扩散到存储器件中。

公开(公告)号：US06710381B1

公开(公告)日：2004-03-23

申请号：US10065355

申请日：2002-10-08

申请人： Weng-Hsing Huang ,  Kent Kuohua Chang

发明人： Weng-Hsing Huang ,  Kent Kuohua Chang

IPC分类号： H01L29749

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/115

摘要： The present invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate structure disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate structures; a raised line disposed on the burled bit line; an isolating spacer disposed on both sidewalls of the gate structure and a word line disposed over the substrate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the raised line and the word line.

摘要翻译： 本发明提供了一种存储器结构，包括：衬底; 设置在所述基板的一部分上的栅极氧化物层; 设置在所述栅极氧化物层上的栅极结构; 沿栅极结构的两侧设置在衬底中的掩埋位线; 布置在钻头位线上的凸起线; 设置在所述栅极结构的两个侧壁上的隔离间隔物和在垂直于所述掩埋位线的方向上设置在所述基板上的字线; 以及设置在所述凸起线的顶部上以将所述凸起线和所述字线电隔离的绝缘层。

公开(公告)号：US06620698B1

公开(公告)日：2003-09-16

申请号：US10245588

申请日：2002-09-18

申请人： Chao-Yang Chen ,  Kent Kuohua Chang

发明人： Chao-Yang Chen ,  Kent Kuohua Chang

IPC分类号： H01L27108

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/76895 ,  H01L27/10882

摘要： This invention relates to a method for manufacturing a flash memory, more particularly, to the method for manufacturing the contact in a flash memory with buried conductive line. The method uses an ion implantation process to form buried conductive lines under isolation regions such as shallow trench isolations. Then a dielectric layer is formed on the buried conductive line and the contact, whose top is wider than the bottom, is formed in the dielectric layer. At last, a polysilicon layer is formed in the contact to connect with different devices, which are in the different layers. The buried conductive lines connect neighboring active regions and replace conventional contacts and lead lines connecting the active regions. The bottom of the contact and the buried conductive line are connected with each other.

摘要翻译： 本发明涉及一种用于制造闪速存储器的方法，更具体地说，涉及在具有埋入导线的闪速存储器中制造接触的方法。 该方法使用离子注入工艺在诸如浅沟槽隔离的隔离区域下形成掩埋导电线。 然后在掩埋导电线上形成电介质层，并且在电介质层中形成其顶部比底部更宽的触点。 最后，在接触件中形成多晶硅层，以连接在不同的层中的不同器件。 掩埋的导线连接相邻的有源区，并代替连接有源区的常规触点和引线。 触点的底部和埋入的导线彼此连接。

公开(公告)号：US06602805B2

公开(公告)日：2003-08-05

申请号：US09735894

申请日：2000-12-14

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： In fabricating nitride read only memory, a zirconium oxide layer has high dielectric constant and a zirconium oxide layer is replaced conventional tunnel oxide layer. Zirconium oxide layer can increase coupling ratio of gate dielectric layer and reliability for nitride read only memory type flash memory is improved. This invention, a substrate is provided and a zirconium oxide layer is formed on substrate by reactive magnetron sputtering and a silicon nitride layer is sandwiched between a zirconium oxide layer and a silicon oxide layer. Then, an ONO layer (oxide-nitride-oxide layer) is formed. The method is using zirconium oxide as gate dielectric can reduce leakage current, increase drain current, improve subthreshold characteristics, and electron and hole mobilities.

公开(公告)号：US06551879B1

公开(公告)日：2003-04-22

申请号：US10101931

申请日：2002-03-21

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L218247

CPC分类号： H01L21/0217 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02351 ,  H01L21/28273 ,  H01L21/3144 ,  H01L21/31612 ,  Y10S438/981

摘要： A method for forming a semiconductor device that includes defining a substrate to include a peripheral section and a core section, masking the peripheral section of the substrate, growing a first dielectric layer over the core section of the substrate, depositing a first polysilicon layer over the first dielectric layer for forming at least one gate structure, growing a first oxide layer over the first polysilicon layer, depositing a nitride layer over the first oxide layer, implanting oxygen ions into the nitride layer, unmasking the peripheral section of the substrate, and growing a second oxide layer over the nitride layer, wherein the growth rate of the second oxide layer is increased due to the implantation of oxygen ions in the nitride layer.

摘要翻译： 一种用于形成半导体器件的方法，包括限定衬底以包括外围部分和芯部分，掩蔽衬底的周边部分，在衬底的芯部上生长第一电介质层，在衬底的芯部上沉积第一多晶硅层 用于形成至少一个栅极结构的第一介电层，在所述第一多晶硅层上生长第一氧化物层，在所述第一氧化物层上沉积氮化物层，将氧离子注入到所述氮化物层中，对所述衬底的外围部分进行屏蔽， 在氮化物层上的第二氧化物层，其中由于在氮化物层中注入氧离子，第二氧化物层的生长速率增加。

公开(公告)号：US06541322B2

公开(公告)日：2003-04-01

申请号：US09858512

申请日：2001-05-17

申请人： Kent Kuohua Chang

发明人： Kent Kuohua Chang

IPC分类号： H01L218238

CPC分类号： H01L21/28044 ,  H01L29/4925

摘要： The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The method involves first forming a silicon oxide layer on the substrate. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si1-xGex, x=0.05˜1.0) layer on the amorphous silicon layer. Thereafter, an etching process removes portions of the silicon germanium layer and the amorphous silicon layer so as to form gates of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.

公开(公告)号：US06486028B1

公开(公告)日：2002-11-26

申请号：US09990459

申请日：2001-11-20

申请人： Kent Kuohua Chang ,  Yao-Wen Chang

发明人： Kent Kuohua Chang ,  Yao-Wen Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A method for fabricating a nitride read only device is disclosed. A trench is formed in a semiconductor substrate. An ion implantation is performed to form a first source/drain region and a second source/drain region within the substrate in the upper corners of the trench, and to form a common source/drain region within the substrate at a bottom of the trench. Next, a trapping layer is formed over the substrate and the trench and a gate conducting layer is formed over the substrate and filling the trench.

摘要翻译： 公开了一种制造氮化物只读器件的方法。 在半导体衬底中形成沟槽。 执行离子注入以在沟槽的上角中的衬底内形成第一源极/漏极区域和第二源极/漏极区域，并且在沟槽的底部在衬底内形成公共源极/漏极区域。 接下来，在衬底上形成捕获层，并且在衬底上形成沟槽和栅极导电层，并填充沟槽。