公开(公告)号：US06461949B1

公开(公告)日：2002-10-08

申请号：US09820305

申请日：2001-03-29

申请人： Kent Kuohua Chang ,  Chia-Hsing Chen

发明人： Kent Kuohua Chang ,  Chia-Hsing Chen

IPC分类号： H01L214763

CPC分类号： H01L27/11568 ,  H01L21/3143 ,  H01L27/115

摘要： The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.

摘要翻译： 本发明提供一种在半导体晶片中制造氮化物只读存储器（NROM）的改进栅极的方法。 首先在半导体晶片中的硅衬底的表面上分别形成底部氧化物和氮化硅层，然后在300mTorr和200-650的条件下注入五乙氧基钽（Ta（OC 2 H 5）5） 以形成作为顶部氧化物层的五氧化钽（Ta 2 O 5）层。 顶部氧化物层，氮化硅层和底部氧化物层构成氧化物 - 氧化物 - 氧化物（ONO）电介质结构。 最后，在ONO结构的表面上形成栅极导体层，以完成本发明的NROM的制造。 五氧化二钽具有高介电常数，用于降低控制栅极电压和热预算，以增加半导体晶片的耦合比和产率。

公开(公告)号：US06455896B1

公开(公告)日：2002-09-24

申请号：US09840898

申请日：2001-04-25

申请人： Ming-Hung Chou ,  Chia-Hsing Chen ,  Smile Huang ,  Cheng-Jye Liu

发明人： Ming-Hung Chou ,  Chia-Hsing Chen ,  Smile Huang ,  Cheng-Jye Liu

IPC分类号： H01L2362

CPC分类号： H01L27/0255

摘要： The present invention provides a protection circuit comprising one diode wherein the diode is formed by diffusing a heavily doped material of a first conductivity type into a first region of a second conductivity type. An integrated circuit, such as a memory array, is coupled to the diode. The other diode back-to-back is coupled to the diode wherein the other diode is formed by diffusing a heavily doped material of the second conductivity type into the first region and a second region of the first conductivity type. The two diodes in series are capable of discharging for the memory array during manufacturing process.

摘要翻译： 本发明提供了一种包括一个二极管的保护电路，其中二极管通过将第一导电类型的重掺杂材料扩散到第二导电类型的第一区域而形成。 诸如存储器阵列的集成电路耦合到二极管。 另一个二极管背对背耦合到二极管，其中通过将第二导电类型的重掺杂材料扩散到第一区域和第一导电类型的第二区域中而形成另一二极管。 串联的两个二极管能够在制造过程中对存储器阵列进行放电。

公开(公告)号：US06468864B1

公开(公告)日：2002-10-22

申请号：US09927645

申请日：2001-08-10

申请人： Jiann-Long Sung ,  Chen-Chin Liu ,  Chia-Hsing Chen

发明人： Jiann-Long Sung ,  Chen-Chin Liu ,  Chia-Hsing Chen

IPC分类号： H01L21331

CPC分类号： H01L29/66833 ,  H01L29/792

摘要： A method of fabricating silicon nitride read only memory. A trapping layer is formed on a substrate. Next, a patterned photoresist layer is formed, and the substrate region at the lower section of the trapping layer masked by the photoresist layer is defined as a channel region. The substrate region at the lower section of the trapping layer and no masked by the photoresist layer is defined as a source/drain region. Next, a pocket ion implantation is performed while using the photoresist layer as amask, and a first dopant is implanted into the source/drain region of the substrate. The photoresist layer is used as a mask and the source/drain ions are implanted. A second dopant is implanted into the source/drain region of the substrate. After that, the photoresist layer is removed. Next, the trapping layer is used as a mask, and a thermal process is performed so that the substrate surface of the source/drain region forms a buried source/drain oxide layer, while at the same time, the second dopant at the lower section of the buried source/drain oxide layer forms a buried source/drain. The first dopant forms the pocket doping region at the edge of the channel region of the buried source/drain periphery as a result of thermal diffusion. Finally, a conductive gate is formed on the substrate.

摘要翻译： 一种制造氮化硅只读存储器的方法。 在基板上形成捕获层。 接下来，形成图案化的光致抗蚀剂层，并且由光致抗蚀剂层掩蔽的捕获层的下部的基板区域被定义为沟道区域。 捕获层的下部的基板区域被光致抗蚀剂层掩蔽，被定义为源极/漏极区域。 接下来，使用光致抗蚀剂层作为掩模进行袋式离子注入，并且将第一掺杂剂注入到衬底的源极/漏极区域中。 光致抗蚀剂层用作掩模，并且注入源/漏离子。 将第二掺杂剂注入到衬底的源极/漏极区域中。 之后，去除光致抗蚀剂层。 接下来，将捕获层用作掩模，并且进行热处理，使得源极/漏极区域的衬底表面形成掩埋源极/漏极氧化物层，同时在下部的第二掺杂剂 的掩埋源极/漏极氧化物层形成埋入的源极/漏极。 作为热扩散的结果，第一掺杂剂在掩埋源极/漏极周边的沟道区域的边缘处形成腔体掺杂区域。 最后，在基板上形成导电栅极。

公开(公告)号：US20100213528A1

公开(公告)日：2010-08-26

申请号：US12776204

申请日：2010-05-07

申请人： Chia-Hsing Chen

发明人： Chia-Hsing Chen

IPC分类号： H01L29/78 ,  H01L29/792 ,  H01L29/788

CPC分类号： G11C16/0483 ,  H01L21/8221 ,  H01L27/0694 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/7838

摘要： The present invention discloses a metal oxide semiconductor (MOS) device and a method for operating an array structure comprising the same devices. The MOS device of the present invention comprises a device layer; an ion-implanted layer formed on the device layer and providing the source, the drain and the channel; and a gate structure formed on the ion-implanted layer. Via applying a bias voltage to the gate, the carrier density in the channel region is different from that in the source region or the drain region; thereby, the MOS device of the present invention can undertake programming, erasing and reading activities. The present invention can simplify the MOS device fabrication process, reduce the operating voltage, and promote the integration density of a 2-dimensional or 3-dimensional MOS device array.

摘要翻译： 本发明公开了一种金属氧化物半导体（MOS）器件和一种用于操作包括相同器件的阵列结构的方法。 本发明的MOS器件包括器件层; 形成在器件层上并提供源极，漏极和沟道的离子注入层; 以及形成在离子注入层上的栅极结构。 通过向栅极施加偏置电压，沟道区域中的载流子密度不同于源极区域或漏极区域中的载流子密度; 因此，本发明的MOS器件可进行编程，擦除和阅读活动。 本发明可以简化MOS器件制造工艺，降低工作电压，并且提高二维或三维MOS器件阵列的集成密度。

公开(公告)号：US06757193B2

公开(公告)日：2004-06-29

申请号：US10115799

申请日：2002-04-03

申请人： Chia-Hsing Chen ,  Cheng-Jye Liu

发明人： Chia-Hsing Chen ,  Cheng-Jye Liu

IPC分类号： G11C1604

CPC分类号： G11C11/5628 ,  G11C7/1006 ,  G11C11/56

摘要： A coding method of a multi-level cell, applied to a programming operation of a multi-level memory cell. The multi-level memory cell can store n bits and has 2n levels with respect to 2n codes. Each code is constructed with n bits. In the coding method, a code to be stored is provided. According to a relationship between the code and level, the multi-level memory cell has a specified level for corresponding code to be stored. The relationship is a correspondence between the 2n codes and the 2n levels. Two codes corresponding to any neighboring two levels has only a one-bit difference.

摘要翻译： 一种应用于多层存储单元的编程操作的多级单元的编码方法。 多级存储器单元可以存储n位，并且相对于2 代码具有2 电平。 每个代码由n位构成。 在编码方法中，提供要存储的代码。 根据代码和级别之间的关系，多级存储器单元具有用于存储的相应代码的指定级别。 关系是2 代码和2 级之间的对应关系。 对应于任何相邻两个级别的两个代码仅具有一位差。

公开(公告)号：US06608499B2

公开(公告)日：2003-08-19

申请号：US10128717

申请日：2002-04-23

申请人： Tseng-Yi Liu ,  Han-Sung Chen ,  Cheng-Jye Liu ,  Chia-Hsing Chen ,  Chun-Hsiung Hung

发明人： Tseng-Yi Liu ,  Han-Sung Chen ,  Cheng-Jye Liu ,  Chia-Hsing Chen ,  Chun-Hsiung Hung

IPC分类号： H03K1923

CPC分类号： G11C16/3427 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3418

摘要： A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed, wherein the the word line voltages are arbitrated according to the threshold voltages of the neighbor bits adjacent to the bits. Next, the bits, to which a same word line voltage should be applied, in the memory cells are distributed to a group of bits with the same word line voltage. Then, the same word line voltage is applied to the bits of the group of bits with the same word line voltage.

摘要翻译： 提供了用于补偿相邻位的阈值电压的方法。 该方法包括对施加到要编程的位的字线电压进行仲裁的第一步骤，其中根据与位相邻的相邻位的阈值电压对字线电压进行仲裁。 接下来，在存储器单元中应该施加相同字线电压的位被分配到具有相同字线电压的一组位。 然后，相同的字线电压被加到具有相同字线电压的位组中。

公开(公告)号：US06562548B2

公开(公告)日：2003-05-13

申请号：US09871211

申请日：2001-05-31

申请人： Chia-Hsing Chen ,  Liu Cheng-Jye ,  Tai-Liang Hsiung

发明人： Chia-Hsing Chen ,  Liu Cheng-Jye ,  Tai-Liang Hsiung

IPC分类号： G03C556

CPC分类号： H01L27/1126 ,  H01L21/2652 ,  H01L27/112

摘要： A fabrication method for a mask read-only memory includes forming an oxide layer on a provided substrate. A first mask layer is formed on the oxide layer, followed by performing a first ion implantation to form a plurality of equally spaced bit lines. A thermal process is further conducted to convert the oxide layer to a denser oxide layer. A plurality of word lines, which is perpendicular to the bit lines, is formed on the denser oxide layer. A second mask layer is formed on the plurality of the word lines, exposing the channel to be coded. A second ion implantation is conducted on the channel to complete the fabrication of the mask read-only memory device.

公开(公告)号：US06448101B1

公开(公告)日：2002-09-10

申请号：US09683382

申请日：2001-12-20

申请人： Tung-Cheng Kuo ,  Chia-Hsing Chen ,  Samuel Cheng-Sheng Pan

发明人： Tung-Cheng Kuo ,  Chia-Hsing Chen ,  Samuel Cheng-Sheng Pan

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  H01L27/14609 ,  H01L27/14689 ,  Y10S438/981

摘要： A method of integrating a photodiode and a CMOS transistor with a NVM on a semiconductor substrate is provided. A photo sensor region, a periphery circuit region, and a memory cell region are defined on the substrate. A first doped area is formed within the semiconductor substrate in the periphery circuit region, the photo sensor region and the memory cell region. A second doped area is formed within the semiconductor substrate in the periphery circuit region. An ONO dielectric layer is formed on the surface of the semiconductor substrate. A third doped area is formed on the first doped area in the photo sensor region, and a fourth doped area is formed on the first doped area in the memory cell region. Following removal of portions of the ONO dielectric layer covering the fourth doped region in the photo sensor region, the periphery circuit region and the memory cell region, an oxide layer is formed on the first doped area, the second doped area, the third doped area, and the fourth doped area. A plurality of gates is formed in the periphery circuit region and in the memory cell region, and a source and a drain are formed in the periphery circuit region.

摘要翻译： 提供了一种在半导体衬底上将光电二极管和CMOS晶体管与NVM集成的方法。 在基板上限定光传感器区域，外围电路区域和存储单元区域。 第一掺杂区域形成在外围电路区域，光传感器区域和存储单元区域中的半导体衬底内。 在外围电路区域内的半导体衬底内形成第二掺杂区域。 在半导体衬底的表面上形成ONO电介质层。 第三掺杂区域形成在光传感器区域中的第一掺杂区域上，并且第四掺杂区域形成在存储单元区域中的第一掺杂区域上。 在除去覆盖光传感器区域中的第四掺杂区域，外围电路区域和存储单元区域的ONO介电层的部分之后，在第一掺杂区域，第二掺杂区域，第三掺杂区域上形成氧化物层 ，和第四掺杂区域。 在周边电路区域和存储单元区域中形成多个栅极，在外围电路区域形成源极和漏极。

公开(公告)号：US6040993A

公开(公告)日：2000-03-21

申请号：US28229

申请日：1998-02-23

申请人： Chia-Hsing Chen ,  Mam-Tsung Wang

发明人： Chia-Hsing Chen ,  Mam-Tsung Wang

IPC分类号： G11C11/56 ,  G11C27/00 ,  G11C7/00

CPC分类号： G11C16/3486 ,  G11C11/5621 ,  G11C11/5628 ,  G11C27/005 ,  G11C2211/5642

摘要： A method for programming an analog/multi-level flash memory array, which insures fast programming to substantially all of the cells in the array, without over-programming, is based on providing a pattern of program retry pulses which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes three stages which program and verify cell threshold voltages with different program verification margins so that an accurate cell threshold voltage can be achieved for each cell.

摘要翻译： 一种用于编程模拟/多级闪存阵列的方法，其基于提供具有相应脉冲宽度和脉冲的程序重试脉冲的模式，确保快速编程到阵列中的基本上所有的阵列中的单元，而不需要过度编程 高度根据模式而变化。 该模式包括三个阶段，其编程和验证具有不同程序验证余量的单元阈值电压，使得可以为每个单元实现精确的单元阈值电压。

公开(公告)号：US08930866B2

公开(公告)日：2015-01-06

申请号：US13794024

申请日：2013-03-11

申请人： Hung-Cheng Sung ,  Yue-Der Chih ,  Chia-Hsing Chen

发明人： Hung-Cheng Sung ,  Yue-Der Chih ,  Chia-Hsing Chen

IPC分类号： G06F17/50 ,  H01L29/66

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/06 ,  G06F2217/78 ,  H01L27/0207 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference.

摘要翻译： 一种设计电荷俘获存储器阵列的方法，包括设计浮栅存储器阵列布局。 浮动栅极存储器布局包括第一类型的晶体管，浮动栅极存储器阵列布局的存储器单元之间的电连接，第一输入/输出（I / O）接口，第一类型的电荷泵和I / O块 。 该方法还包括使用处理器来修改浮动栅极存储器阵列布局，以用与第一类型的晶体管不同的第二类型的晶体管代替第一类型的晶体管。 该方法还包括确定I / O块和第二类型的晶体管之间的工作电压差。 该方法还包括使用处理器修改浮动栅极存储器阵列布局，以基于所确定的工作电压差来修改第一电荷泵。