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53 条记录 (耗时 0.032 秒)

    Integrated circuit system with band to band tunneling and method of manufacture thereof
    41.
    发明授权
    Integrated circuit system with band to band tunneling and method of manufacture thereof 有权
    具有带对隧道的集成电路系统及其制造方法

    公开(公告)号：US09159565B2

    公开(公告)日：2015-10-13

    申请号：US12544747

    申请日：2009-08-20

    申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

    发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

    IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L21/265

    CPC分类号： H01L21/26586 ,  H01L29/34 ,  H01L29/66356 ,  H01L29/7391

    摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

    摘要翻译： 一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

    Control gate
    42.
    发明授权
    Control gate 有权
    控制门

    公开(公告)号：US08647946B2

    公开(公告)日：2014-02-11

    申请号：US12621527

    申请日：2009-11-19

    申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Chunshan Yin

    发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Chunshan Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42364 ,  B82Y10/00 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/1045 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation.

    摘要翻译： 公开了一种用于形成半导体器件的方法。 该方法包括提供用第二栅极结构制备的衬底。 在衬底上并在第二栅极上形成栅极间电介质。 还形成了第一道门。 第一栅极通过栅极间电介质相邻并与第二栅极分离。 图案化衬底以形成具有第一和第二相邻栅极的分离栅极结构。 分离栅极结构设置有与第一栅极相邻的电场均衡器。 电场均衡器在操作期间改善了第一栅极电场的均匀性。

    Method of forming source and drain of field-effect-transistor and structure thereof
    45.
    发明授权
    Method of forming source and drain of field-effect-transistor and structure thereof 失效
    形成场效应晶体管的源极和漏极的方法及其结构

    公开(公告)号：US08138053B2

    公开(公告)日：2012-03-20

    申请号：US11763561

    申请日：2007-06-15

    申请人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

    发明人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

    摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

    摘要翻译： 本发明的实施例提供了形成场效应晶体管（FET）的方法。 该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。 还提供了由其制成的半导体场效应晶体管的结构。

    STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING
    46.
    发明申请
    STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING 审中-公开
    应变直接绝缘体（SDOI）基板和形成方法

    公开(公告)号：US20110278645A1

    公开(公告)日：2011-11-17

    申请号：US13191288

    申请日：2011-07-26

    申请人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

    发明人： Lee Wee Teo ,  Chung Foong Tan ,  Shyue Seng Tan ,  Elgin Quek

    IPC分类号： H01L29/165

    CPC分类号： H01L29/165 ,  H01L21/76254 ,  H01L29/1054 ,  Y10S438/933

    摘要： Methods (and semiconductor substrates produced therefrom) of fabricating (n−1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n−1 SDOI substrates.

    摘要翻译： 描述了使用n个晶片制造（n-1）个SDOI衬底的方法（以及由此制备的半导体衬底）。 施主衬底（例如，硅）包括缓冲层（例如，SiGe）和形成在其上的多个交替应力（例如，弛豫SiGe）和应变（例如硅）层的多层叠层。 绝缘体邻近最外层应变硅层设置。 最外层的应变硅层和下面的松弛的SiGe层通过常规或已知的粘结和分离方法转移到处理衬底。 处理手柄基板以去除松弛的SiGe层，从而产生用于进一步使用的SDOI基板。 处理剩余的施主衬底以除去一层或多层以暴露另一应变硅层。 重复各种处理步骤以产生另一个SDOI衬底以及剩余的施主衬底，并且可以重复该步骤以产生n-1个SDOI衬底。

    INTEGRATED CIRCUIT SYSTEM WITH BAND TO BAND TUNNELING AND METHOD OF MANUFACTURE THEREOF
    49.
    发明申请
    INTEGRATED CIRCUIT SYSTEM WITH BAND TO BAND TUNNELING AND METHOD OF MANUFACTURE THEREOF 有权
    带对带隧道的集成电路系统及其制造方法

    公开(公告)号：US20110042757A1

    公开(公告)日：2011-02-24

    申请号：US12544747

    申请日：2009-08-20

    申请人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

    发明人： Shyue Seng Tan ,  Lee Wee Teo ,  Ming Zhu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/34 ,  H01L29/66356 ,  H01L29/7391

    摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.

    摘要翻译： 一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

    Modulation of stress in stress film through ion implantation and its application in stress memorization technique
    50.
    发明授权
    Modulation of stress in stress film through ion implantation and its application in stress memorization technique 有权
    通过离子注入调制应力薄膜中的应力及其在应力记忆技术中的应用

    公开(公告)号：US07592270B2

    公开(公告)日：2009-09-22

    申请号：US11940326

    申请日：2007-11-15

    申请人： Lee Wee Teo ,  Elgin Quek

    发明人： Lee Wee Teo ,  Elgin Quek

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/469 ,  H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.

    摘要翻译： 本发明的一些示例性实施例提供了一种通过增加通道区域中的应力来改善MOS器件的性能的方法。 用于NMOS晶体管的示例性实施例是在NMOS晶体管上形成拉伸应力层。 对应力层进行重离子注入，然后进行退火。 这增加了由栅极保持/存储的应力层的应力量，从而提高了器件性能。