公开(公告)号：US6162587A

公开(公告)日：2000-12-19

申请号：US203450

申请日：1998-12-01

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  G03C5/00

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

公开(公告)号：US6140023A

公开(公告)日：2000-10-31

申请号：US203447

申请日：1998-12-01

申请人： Harry J. Levinson ,  Scott A. Bell ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

发明人： Harry J. Levinson ,  Scott A. Bell ,  Christopher F. Lyons ,  Khanh B. Nguyen ,  Fei Wang ,  Chih Yuh Yang

IPC分类号： G03F7/075 ,  G03F7/40 ,  G03F9/00

CPC分类号： G03F7/405 ,  G03F7/075 ,  G03F7/40

摘要： A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresist is oxidized so as to convert the silicon therein to silicon dioxide. The oxidized ultra-thin photoresist layer is used as a hard mask during an etch step to transfer the pattern to the underlayer. The etch step includes an etch chemistry that is highly selective to the underlayer over the oxidized ultra-thin photoresist layer.

摘要翻译： 提供了用于制造亚微米特征的光刻工艺。 在要蚀刻的底层表面上形成含硅的超薄光致抗蚀剂。 用短波长辐射图案化超薄光致抗蚀剂层以限定图案。 超薄光致抗蚀剂被氧化以将其中的硅转化为二氧化硅。 氧化的超薄光致抗蚀剂层在蚀刻步骤期间用作硬掩模以将图案转印到底层。 蚀刻步骤包括对氧化的超薄光致抗蚀剂层上的底层具有高选择性的蚀刻化学品。

公开(公告)号：US6127070A

公开(公告)日：2000-10-03

申请号：US203283

申请日：1998-12-01

申请人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

发明人： Chih Yuh Yang ,  Christopher F. Lyons ,  Harry J. Levinson ,  Khanh B. Nguyen ,  Fei Wang ,  Scott A. Bell

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0274 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a nitride layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the nitride layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer and the dielectric layer. The nitride layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在电介质层上形成氮化物层。 在氮化物层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行图案化，以形成通孔图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转移到氮化物层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的氮化物层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，氮化物层用作硬掩模，以通过蚀刻介电层的部分来形成与通孔图案相对应的接触孔。

公开(公告)号：US09093481B2

公开(公告)日：2015-07-28

申请号：US11789157

申请日：2007-04-23

申请人： Harry J. Levinson

发明人： Harry J. Levinson

IPC分类号： H01L21/02 ,  H01L21/67 ,  G03F7/20

CPC分类号： H01L21/67028 ,  G03F7/70925 ,  H01L21/02057 ,  H01L21/67011

摘要： In one disclosed embodiment, the present method for semiconductor fabrication utilizing a cleaning substrate comprises loading a cleaning substrate capable of removing an undesirable particle from a semiconductor processing tool onto the tool, causing the undesirable particle to be attracted to the cleaning substrate, and unloading the cleaning substrate from the semiconductor processing tool. Following cleaning, the processing tool can be used for producing a lithographic pattern on a semiconductor wafer. In one embodiment, the cleaning substrate comprises an electret. In another embodiment, the cleaning substrate comprises an adhesive layer. The present method can be used without breaking vacuum, or otherwise altering the operational state of a processing tool. In one embodiment, the present method is used in conjunction with an exposure tool utilized for high resolution lithography, for example, an extreme ultraviolet (EUV) lithographic exposure tool.

摘要翻译： 在一个公开的实施例中，本发明使用清洁基板的半导体制造方法包括将能够从半导体加工工具移除不需要的颗粒的清洁基板装载到工具上，使不期望的颗粒被吸引到清洁基板上， 从半导体处理工具清洁基板。 在清洁之后，处理工具可用于在半导体晶片上制造平版印刷图案。 在一个实施例中，清洁基板包括驻极体。 在另一个实施例中，清洁衬底包括粘合剂层。 本方法可以在不破坏真空的情况下使用，或以其它方式改变加工工具的操作状态。 在一个实施例中，本方法与用于高分辨率光刻的曝光工具结合使用，例如极紫外（EUV）光刻曝光工具。

公开(公告)号：US08792161B2

公开(公告)日：2014-07-29

申请号：US11709718

申请日：2007-02-21

申请人： Bruno M. LaFontaine ,  Ryoung-Han Kim ,  Harry J. Levinson ,  Uzodinma Okoroanyanwu

发明人： Bruno M. LaFontaine ,  Ryoung-Han Kim ,  Harry J. Levinson ,  Uzodinma Okoroanyanwu

IPC分类号： G02B5/30

CPC分类号： G02B5/3058 ,  G02B5/3075 ,  G02F1/0136 ,  G03F7/70566

摘要： An optical polarizer positioned before a light source for use in semiconductor wafer lithography including an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.

摘要翻译： 位于用于半导体晶片光刻的光源之前的光学偏振器，包括排列的纳米管阵列。 排列的纳米管的阵列引起从光源发射并入射到排列的纳米管阵列上的光，以转换为偏光，用于半导体晶片光刻。 极化量可以通过耦合到排列的纳米管阵列的电压源来控制。 光过滤层的显色材料可以改变通过排列的纳米管阵列传输的偏振光的波长。

公开(公告)号：US08586269B2

公开(公告)日：2013-11-19

申请号：US11726433

申请日：2007-03-22

申请人： Uzodinma Okoroanyanwu ,  Harry J. Levinson ,  Ryoung-Han Kim ,  Thomas Wallow

发明人： Uzodinma Okoroanyanwu ,  Harry J. Levinson ,  Ryoung-Han Kim ,  Thomas Wallow

IPC分类号： G11B11/105

CPC分类号： G03F7/38

摘要： In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.

摘要翻译： 在一个公开的实施例中，在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。 在一个实施例中，图案化的辐射由极紫外（EUV）光源提供。 在其它实施例中，图案化辐射源可以是例如电子束或离子束。 在一个实施方案中，聚合物基质是有机聚合物基质，例如苯乙烯，丙烯酸酯或甲基丙烯酸酯。 在一个实施方案中，催化物质可以是例如酸，碱或氧化剂。

公开(公告)号：US08067252B2

公开(公告)日：2011-11-29

申请号：US11706118

申请日：2007-02-13

申请人： Yuansheng Ma ,  Harry J. Levinson ,  Thomas Wallow

发明人： Yuansheng Ma ,  Harry J. Levinson ,  Thomas Wallow

IPC分类号： H01L21/66

CPC分类号： G03F7/70625 ,  G03F7/705 ,  G03F7/70616

摘要： According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes determining an autoregressive estimation of the edge of the at least one patterned feature using measured data corresponding to a number of points on the edge. The method further includes determining a power spectral density of the edge using autoregressive coefficients from the autoregressive estimation. The method further includes utilizing the power spectral density to characterize line edge roughness of the at least one patterned feature in a frequency domain.

摘要翻译： 根据一个示例性实施例，用于确定位于半导体晶片之上的至少一个图案化特征的边缘的功率谱密度的方法包括在边缘上的多个点处测量所述至少一个图案化特征的边缘。 该方法还包括使用与边缘上的多个点对应的测量数据来确定至少一个图案化特征的边缘的自回归估计。 该方法还包括使用来自自回归估计的自回归系数确定边缘的功率谱密度。 该方法还包括利用功率谱密度来表征频域中的至少一个图案化特征的线边缘粗糙度。

公开(公告)号：US07563560B1

公开(公告)日：2009-07-21

申请号：US11047840

申请日：2005-02-01

申请人： Adam R. Pawloski ,  Harry J. Levinson

发明人： Adam R. Pawloski ,  Harry J. Levinson

IPC分类号： G03F7/26

CPC分类号： G03F7/0048 ,  G03F7/2041

摘要： A polyelectrolyte solution for tuning a surface energy and a method for using the polyelectrolyte solution to manufacture an integrated circuit. A substrate is provided and a photosensitive material having a surface energy is formed over the substrate. The substrate may be polysilicon, silicon dioxide, silicon nitride, metal, and the like. The photosensitive material is treated with a polyelectrolyte solution to change the surface energy of the photosensitive material. Treatment techniques for applying the polyelectrolyte solution may include spraying, bathing, rinsing, soaking, or washing. The polyelectrolyte adsorbs to the photosensitive material forming a polyelectrolyte polymer layer on the photosensitive material. The photosensitive material may be a photoresist or a photoresist having a topcoat formed thereon. The photosensitive material is exposed using lithography techniques and processed to form a patterned layer of photosensitive material for use in manufacturing the integrated circuit.

摘要翻译： 用于调谐表面能的聚电解质溶液和使用聚电解质溶液制造集成电路的方法。 提供衬底，并且在衬底上形成具有表面能的感光材料。 衬底可以是多晶硅，二氧化硅，氮化硅，金属等。 感光材料用聚电解质溶液处理以改变感光材料的表面能。 施加聚电解质溶液的处理技术可包括喷雾，洗澡，漂洗，浸泡或洗涤。 聚电解质吸附在感光材料上形成聚电解质聚合物层。 感光材料可以是其上形成有顶涂层的光致抗蚀剂或光致抗蚀剂。 感光材料使用光刻技术曝光并被处理以形成用于制造集成电路的感光材料的图案化层。

公开(公告)号：US20080257383A1

公开(公告)日：2008-10-23

申请号：US11789157

申请日：2007-04-23

申请人： Harry J. Levinson

发明人： Harry J. Levinson

IPC分类号： B08B7/04

CPC分类号： H01L21/67028 ,  G03F7/70925 ,  H01L21/02057 ,  H01L21/67011

摘要： In one disclosed embodiment, the present method for semiconductor fabrication utilizing a cleaning substrate comprises loading a cleaning substrate capable of removing an undesirable particle from a semiconductor processing tool onto the tool, causing the undesirable particle to be attracted to the cleaning substrate, and unloading the cleaning substrate from the semiconductor processing tool. Following cleaning, the processing tool can be used for producing a lithographic pattern on a semiconductor wafer. In one embodiment, the cleaning substrate comprises an electret. In another embodiment, the cleaning substrate comprises an adhesive layer. The present method can be used without breaking vacuum, or otherwise altering the operational state of a processing tool. In one embodiment, the present method is used in conjunction with an exposure tool utilized for high resolution lithography, for example, an extreme ultraviolet (EUV) lithographic exposure tool.

摘要翻译： 在一个公开的实施例中，本发明使用清洁基板的半导体制造方法包括将能够从半导体加工工具移除不需要的颗粒的清洁基板装载到工具上，使不期望的颗粒被吸引到清洁基板上， 从半导体处理工具清洁基板。 在清洁之后，处理工具可用于在半导体晶片上制造平版印刷图案。 在一个实施例中，清洁基板包括驻极体。 在另一个实施例中，清洁衬底包括粘合剂层。 本方法可以在不破坏真空的情况下使用，或以其他方式改变加工工具的操作状态。 在一个实施例中，本方法与用于高分辨率光刻的曝光工具结合使用，例如极紫外（EUV）光刻曝光工具。

公开(公告)号：US20080124820A1

公开(公告)日：2008-05-29

申请号：US11606440

申请日：2006-11-29

申请人： Harry J. Levinson ,  Obert Reeves Wood

发明人： Harry J. Levinson ,  Obert Reeves Wood

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G03F7/70916 ,  G03F7/707 ,  H01L21/67288

摘要： One exemplary embodiment is a method for detecting existence of an undesirable particle between a planar lithographic object, such as a semiconductor wafer or a lithographic mask, and a chuck during semiconductor fabrication. The exemplary method in this embodiment includes placing the planar lithographic object, such as the semiconductor wafer, over the chuck. The method further includes measuring a change in at least one electrical characteristic formed by and between the chuck and the planar lithographic object, such as measuring a change in capacitance between the chuck and semiconductor wafer, caused by the undesirable particle.

摘要翻译： 一个示例性实施例是用于在半导体制造期间检测平面光刻物体（例如半导体晶片或光刻掩模）和卡盘之间的不期望的粒子的存在的方法。 该实施例中的示例性方法包括将诸如半导体晶片的平面光刻物体放置在卡盘上。 该方法还包括测量由卡盘和平面光刻物体之间形成的和在平面光刻物体之间形成的至少一个电特性的变化，例如测量卡盘和半导体晶片之间由不期望的粒子引起的电容变化。