公开(公告)号：US08835977B2

公开(公告)日：2014-09-16

申请号：US13720140

申请日：2012-12-19

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Limin Weng

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Limin Weng

IPC分类号： H01L29/866 ,  H01L27/04 ,  H01L27/02 ,  H01L27/08

CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0814 ,  H01L29/866 ,  H01L29/87

摘要： A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.

摘要翻译： 一种设置在第一导电类型的半导体衬底上的瞬态电压抑制（TVS）器件。 TVS包括第二导电类型的掩埋掺杂区域，其被布置和包围在第一导电类型的外延层中，其中掩埋掺杂剂区域横向延伸并且具有与外延层的下面部分接合的延伸的底部接合区域，从而构成 用于TVS器件的齐纳二极管。 TVS器件还包括掩埋掺杂剂区域上方的区域，还包括第二导电类型的顶部掺杂剂层和第二导电类型的顶部接触区域，其与外延层和掩埋掺杂剂区域结合起来以形成多个 连接构成SCR作为转向二极管的PN结与用于抑制瞬态电压的齐纳二极管起作用的PN结。

公开(公告)号：US08829614B2

公开(公告)日：2014-09-09

申请号：US12584151

申请日：2009-08-31

申请人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

发明人： Lingpeng Guan ,  Anup Bhalla ,  Madhur Bobde ,  Tinggang Zhu

IPC分类号： H01L27/12

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66325 ,  H01L29/7395 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

摘要翻译： 本发明公开了一种在半导体衬底中制造半导体功率器件的方法，包括有源电池区域和端接区域。 该方法包括以下步骤：a）在终端区域以及半导体衬底的顶表面上的活性单元区域中生长和构图场氧化物层b）在半导体衬底的顶表面上沉积和构图多晶硅层 在距离场氧化物层的间隙距离处; c）执行空白体掺杂剂注入以在所述半导体衬底中形成与所述间隙区基本对准的体掺杂区，随后将所述体掺杂区扩散到所述半导体衬底中的体区; d）植入包含在并且具有比身体区域更高的掺杂剂浓度的高浓度体 - 掺杂剂区域，以及e）将源掩模施加到具有与身体区域相反的导电性的源极区域，其中源区域包含在身体区域中， 被高浓度体 - 掺杂区域包围。

公开(公告)号：US20140227837A1

公开(公告)日：2014-08-14

申请号：US13763675

申请日：2013-02-10

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/66

CPC分类号： H01L29/66484 ,  H01L29/0634 ,  H01L29/42316 ,  H01L29/66901 ,  H01L29/66909 ,  H01L29/78 ,  H01L29/808

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

摘要翻译： 横向超结JFET由负载在N +衬底上的P表面层上的堆叠的交替P型和N型半导体层形成。 N +漏极柱向下延伸穿过超结结构和P-epi以连接到N +衬底以使器件成为底部漏极器件。 N +源极柱和P +栅极柱延伸穿过超级结，但在P-epi层处停止。 栅极 - 漏极雪崩钳位二极管从P +栅极底部通过P-epi到N +漏极衬底形成。

公开(公告)号：US20140167101A1

公开(公告)日：2014-06-19

申请号：US13720140

申请日：2012-12-19

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Limin Weng

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Limin Weng

IPC分类号： H01L27/04

CPC分类号： H01L27/0259 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0814 ,  H01L29/866 ,  H01L29/87

摘要： A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.

摘要翻译： 一种设置在第一导电类型的半导体衬底上的瞬态电压抑制（TVS）器件。 TVS包括第二导电类型的掩埋掺杂区域，其被布置和包围在第一导电类型的外延层中，其中掩埋掺杂剂区域横向延伸并且具有与外延层的下面部分接合的延伸的底部接合区域，从而构成 用于TVS器件的齐纳二极管。 TVS器件还包括掩埋掺杂剂区域上方的区域，还包括第二导电类型的顶部掺杂剂层和第二导电类型的顶部接触区域，其与外延层和掩埋掺杂剂区域结合起来以形成多个 连接构成SCR作为转向二极管的PN结与用于抑制瞬态电压的齐纳二极管起作用的PN结。

公开(公告)号：US08557671B2

公开(公告)日：2013-10-15

申请号：US13604834

申请日：2012-09-06

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L21/00 ,  H01L29/861

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底被重掺杂;第一导电类型的外延层，形成在衬底上，外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。

公开(公告)号：US08507978B2

公开(公告)日：2013-08-13

申请号：US13162407

申请日：2011-06-16

申请人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

发明人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7806

摘要： An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.

摘要翻译： 集成结构包括多个分离栅沟槽MOSFET。 在碳化硅衬底组合物内形成多个沟槽，每个沟槽衬有钝化层，每个沟槽基本上填充有第一导电区域，第二导电区域和绝缘材料，其介电常数类似于介电常数 碳化硅衬底组合物。 第一导电区域通过绝缘材料与钝化层分离。 第一和第二导电区域形成每个沟槽MOSFET的栅极区域。 第一导电区域通过钝化层与第二导电区域分离。 在衬底组合物的上部形成的第一导电类型的掺杂体区域和形成在掺杂体区域内的第二导电类型的掺杂源区。

公开(公告)号：US08466510B2

公开(公告)日：2013-06-18

申请号：US12610052

申请日：2009-10-30

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7802 ,  H01L29/7811

摘要： A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

摘要翻译： 交错列超结半导体器件可以包括具有一个或多个器件单元的单元区域。 单元区域中的一个或多个器件单元包括被配置为用作漏极的半导体衬底和形成在衬底上的半导体层。 第一掺杂柱可以在半导体层中形成为第一深度，并且第二掺杂柱可以形成在半导体层中至第二深度。 第一个深度大于第二个深度。 第一和第二列掺杂有相同第二导电类型的掺杂剂并且沿着半导体层的厚度的一部分延伸并且由半导体层的一部分分离。

公开(公告)号：US20130075855A1

公开(公告)日：2013-03-28

申请号：US13200683

申请日：2011-09-27

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L29/06 ,  H01L21/22

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

摘要翻译： 一种在半导体基板上制造半导体功率器件的方法，该半导体衬底通过生长第一外延层，然后在外延层的顶部上形成第一硬掩模层，从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤，以形成多个外延层，然后利用扩散处理在外延层的顶侧上进行器件制造工艺，以将掺杂区域 交替导电类型作为外延层中的掺杂列。

公开(公告)号：US08390058B2

公开(公告)日：2013-03-05

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

公开(公告)号：US20120329238A1

公开(公告)日：2012-12-27

申请号：US13604834

申请日：2012-09-06

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L21/302 ,  H01L21/265

CPC分类号： H01L29/861 ,  H01L27/0259 ,  H01L29/10 ,  H01L29/6609

摘要： A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.

摘要翻译： 垂直瞬态电压抑制（TVS）器件包括：第一导电类型的半导体衬底，其中衬底是重掺杂的，第一导电类型的外延层形成在衬底上，其中外延层具有第一厚度;以及基极区 形成在外延层中的第二导电类型，其中基极区位于外延层的中间区域中。 基极区域和外延层在基极区域的两侧提供基本对称的垂直掺杂分布。 在一个实施例中，通过高能量注入形成基极区域。 在另一个实施例中，基底区形成为掩埋层。 选择外延层和基极区域的掺杂浓度以将TVS器件配置为基于穿通二极管的TVS或雪崩模式TVS。