公开(公告)号：US20230360690A1

公开(公告)日：2023-11-09

申请号：US17662198

申请日：2022-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jiyun Li ,  Christopher J. Kawamura ,  Tae H. Kim

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  H03F3/45264

Abstract: Apparatuses, systems, and methods for compensated sense amplifier with crosscoupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

公开(公告)号：US20230197140A1

公开(公告)日：2023-06-22

申请号：US17645253

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Brenton Van Leeuwen ,  Christopher J. Kawamura

IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/06

CPC classification number: G11C11/4085 ,  G11C11/4096 ,  G11C11/4093 ,  G11C5/063

Abstract: Methods of operating memory devices are disclosed. A method may include activating a first, target word line. The method may also include coupling a second word line adjacent the first, target word line to an associated first main word line while the first, target word line is activated. Further, the method may include coupling the associated main word line to a negative word line voltage while the first, target word line is activated. Associated circuits, devices, and systems are also disclosed.

公开(公告)号：US20230084668A1

公开(公告)日：2023-03-16

申请号：US17447490

申请日：2021-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim ,  Christopher J. Kawamura ,  Jiyun Li

IPC: G11C11/4091

Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.

公开(公告)号：US11574668B2

公开(公告)日：2023-02-07

申请号：US17451100

申请日：2021-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US11443780B2

公开(公告)日：2022-09-13

申请号：US17172257

申请日：2021-02-10

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Beau D. Barry ,  Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/32 ,  G11C16/30

Abstract: An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

公开(公告)号：US11211113B1

公开(公告)日：2021-12-28

申请号：US16996741

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4099 ,  G11C11/4076 ,  G11C11/4074

Abstract: Some embodiments include an integrated assembly having first and second wordlines coupled with DRIVER circuitry. The first wordline has a first end distal from the DRIVER circuitry, and the second wordline has a second end distal from the DRIVER circuitry. A switch is adjacent to the first end and is configured to couple said first end to one or both of the second end and a LOW-VOLTAGE-REFERENCE-SOURCE (e.g., a VNWL supply) during a transition of the first wordline from an “ON” state to an “OFF” state.

公开(公告)号：US11205468B2

公开(公告)日：2021-12-21

申请号：US16952439

申请日：2020-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11514 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US11107515B2

公开(公告)日：2021-08-31

申请号：US16937402

申请日：2020-07-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. Derner ,  Christopher J. Kawamura

IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/11502

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

公开(公告)号：US10978138B2

公开(公告)日：2021-04-13

申请号：US17015889

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Christopher J. Kawamura

IPC: G11C7/22 ,  G11C11/408 ,  G11C11/4076

Abstract: A main word line circuit provides a first and second row factor signals. The main word line circuit includes a pull-up circuit to drive a global word line to follow a first decoded address signal when the first row factor signal is at a first value. The main word line circuit includes an intermediate voltage circuit to drive the global word line to follow a value of the second row factor signal. A processing device drives the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and drives the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state.

公开(公告)号：US20210074705A1

公开(公告)日：2021-03-11

申请号：US17083174

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mitsunari Sukekawa ,  Yusuke Yamamoto ,  Christopher J. Kawamura ,  Hiroaki Taketani

IPC: H01L27/108 ,  H01L23/528

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.