公开(公告)号：US12073107B2

公开(公告)日：2024-08-27

申请号：US17378970

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Chun Sum Yeung ,  Kulachet Tanpairoj

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0688

Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

公开(公告)号：US12045482B2

公开(公告)日：2024-07-23

申请号：US17877240

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wai Leong Chin ,  Francis Chee Khai Chew ,  Trismardawi Tanadi ,  Chun Sum Yeung ,  Lawrence Dumalag ,  Ekamdeep Singh

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0646 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7206

Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.

公开(公告)号：US12002531B2

公开(公告)日：2024-06-04

申请号：US17648396

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G06F11/07 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F11/076 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US11829613B2

公开(公告)日：2023-11-28

申请号：US17959844

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method includes receiving, by a processing device, signaling indicative of a power cycle (PC) to a memory device (MD) having a first signal indicative of a Power On Operation and a second signal indicative of a Power Off Operation, and determining an Average Power On Time (APOT) of the MD based, at least in part, on a quantity of power cycles (n) to the MD over a predetermined time interval (PTI), and for each PC over the PTI, an amount of time between receipt of the first signal and the second signal. A sum of each of the amount of time between receipt of the first signal and the second signal in the PTI provides a total power on time (T) to the MD, and the APOT is equal to T/n. When the APOT is less than (

公开(公告)号：US20230049201A1

公开(公告)日：2023-02-16

申请号：US17648396

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/20 ,  G06F11/07

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US20230045990A1

公开(公告)日：2023-02-16

申请号：US17574059

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Chun Sum Yeung ,  Jonathan S. Parry

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.

公开(公告)号：US11556261B2

公开(公告)日：2023-01-17

申请号：US16994213

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Chun Sum Yeung ,  Xiangang Luo

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/20

Abstract: A method includes writing, to a first sub-set of memory blocks of a first plane associated with a memory device, first data corresponding to recovery of an uncorrectable error and writing, to a first sub-set of memory blocks of a second memory plane associated with the memory device, second data corresponding to recovery of the uncorrectable error. A relative physical location of the first sub-set of memory blocks of the first memory plane and a relative physical location of the first sub-set of memory blocks of the second memory plane are a same relative physical location with respect to the first memory plane and the second memory plane.

公开(公告)号：US20220351788A1

公开(公告)日：2022-11-03

申请号：US17243386

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Devin M. Batutis

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

Abstract: A method is described that includes determining, by a memory subsystem controller of a memory device, a number of memory cells from a set of memory cells that are in a programmed state. The memory subsystem controller further compares the number of memory cells from the set of memory cells that are in the programmed state to a proximity disturb threshold and in response to determining that the number satisfies the proximity disturb threshold, performs a remediation operation on user data stored in the set of memory cells.

公开(公告)号：US11456043B2

公开(公告)日：2022-09-27

申请号：US17301743

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Devin M. Batutis ,  Avinash Rajagiri ,  Sheng-Huang Lee ,  Chun Sum Yeung ,  Harish R. Singidi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

公开(公告)号：US20220300374A1

公开(公告)日：2022-09-22

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.