公开(公告)号：US20230335165A1

公开(公告)日：2023-10-19

申请号：US17723798

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C5/14 ,  G11C5/06 ,  H01L25/065

CPC classification number: G11C5/148 ,  G11C5/063 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.

公开(公告)号：US11776625B2

公开(公告)日：2023-10-03

申请号：US17496667

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Hari Giduturi

IPC: G11C13/00 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C13/0038 ,  G11C5/145 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

公开(公告)号：US20230063347A1

公开(公告)日：2023-03-02

申请号：US17461035

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die by a second value.

公开(公告)号：US11430509B2

公开(公告)日：2022-08-30

申请号：US16797432

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C7/00 ,  G11C11/56 ,  G11C29/50 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US20220238157A1

公开(公告)日：2022-07-28

申请号：US17720542

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.

公开(公告)号：US11380411B2

公开(公告)日：2022-07-05

申请号：US17066997

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C16/34 ,  G11C16/20 ,  G11C16/26 ,  G06F9/30 ,  G11C7/22 ,  G06F12/02 ,  G11C7/14

Abstract: A system may include multiple memory cells to store logical data, age tracking circuitry to track a time since a previous access of a particular memory cell, and control circuitry to access the memory cell. Such access may include a read operation of the memory cell, a write operation to the memory cell, or both. The control circuitry may determine an electrical parameter of the memory cell based at least in part on the tracked time since the previous access of the memory cell.

公开(公告)号：US11309023B1

公开(公告)日：2022-04-19

申请号：US17091860

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/00 ,  G11C13/00 ,  G06F9/30

Abstract: A memory system may include multiple memory cells to store logical data and cycle tracking circuitry to track a number of cycles associated the memory cells. The cycles may be representative of one or more past accesses of the memory cells. The memory system may also include control circuitry to access the memory cells. Accessing of the memory cell may include a read operation, a write operation, or both. During the accessing of the memory cell, the control circuitry may determine a voltage parameter of the access based at least in part on the tracked number of cycles.

公开(公告)号：US20220101918A1

公开(公告)日：2022-03-31

申请号：US17549390

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

公开(公告)号：US20220068383A1

公开(公告)日：2022-03-03

申请号：US17005739

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.

公开(公告)号：US20210358545A1

公开(公告)日：2021-11-18

申请号：US15931080

申请日：2020-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.