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    POWER MANAGEMENT
    41.
    发明申请
    POWER MANAGEMENT 有权

    公开(公告)号：US20220392546A1

    公开(公告)日：2022-12-08

    申请号：US17738126

    申请日：2022-05-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Liang Yu ,  Jeremy Binfet

    IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08

    Abstract: A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

    POWER ARCHITECTURE FOR NON-VOLATILE MEMORY
    42.
    发明申请
    POWER ARCHITECTURE FOR NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220254418A1

    公开(公告)日：2022-08-11

    申请号：US17168970

    申请日：2021-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

    IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

    Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

    Separate partition for buffer and snapshot memory
    43.
    发明授权
    Separate partition for buffer and snapshot memory 有权

    公开(公告)号：US11385819B2

    公开(公告)日：2022-07-12

    申请号：US16995682

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

    PEAK POWER MANAGEMENT SELF-CHECK
    44.
    发明申请
    PEAK POWER MANAGEMENT SELF-CHECK 有权

    公开(公告)号：US20220199192A1

    公开(公告)日：2022-06-23

    申请号：US17249400

    申请日：2021-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Jeremy Binfet ,  Liang Yu

    IPC: G11C29/50 ,  G06F1/3225

    Abstract: A memory device includes a first memory die of a plurality of memory dies, the first memory die comprising a first memory array and a first power management component, wherein the first power management component is configured to send a first test value to one or more other power management components on one or more other memory dies of the plurality of memory dies during a first power management cycle of a first power management token loop. The memory device further includes a second memory die of the plurality of memory dies, the second memory die comprising a second memory array and a second power management component, wherein the second power management component is configured to receive the first test value from the first power management component during the first power management cycle of the first power management token loop and send a second test value to the one or more other power management components on the one or more other memory dies of the plurality of memory dies during a second power management cycle of a second power management token loop. At least one of the first power management component or the second power management component is configured to compare the first test value and the second test value to a set of expected values to determine whether signal connections between the first power management component and the second power management component are functional.

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