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    IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES
    41.
    发明申请
    IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES 有权

    公开(公告)号：US20210272615A1

    公开(公告)日：2021-09-02

    申请号：US17325997

    申请日：2021-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Mattia Robustelli ,  Innocenzo Tortorelli ,  Mario Allegra

    IPC: G11C11/16

    Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

    Segregation-based memory
    42.
    发明授权
    Segregation-based memory 有权

    公开(公告)号：US11024372B2

    公开(公告)日：2021-06-01

    申请号：US16102493

    申请日：2018-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Agostino Pirovano ,  Innocenzo Tortorelli

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

    Memory Arrays and Methods of Forming Memory Arrays
    48.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权
    内存数组和形成内存数组的方法

    公开(公告)号：US20150280117A1

    公开(公告)日：2015-10-01

    申请号：US14226643

    申请日：2014-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Andrea Redaelli

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

    Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

    Abstract translation: 一些实施例包括在位线和字线之间垂直地具有多个存储单元的存储器阵列。 存储单元包含相变材料。 热屏蔽沿着位线方向横向位于紧邻的存储单元之间。 隔热罩包含导电材料并与位线电连接。 一些实施例包括具有布置在第一网格中的多个存储单元的存储器阵列。 第一格栅具有沿着第一方向的列，并且沿着与第一方向大致正交的第二方向具有列。 第一热屏蔽沿着第一方向位于相邻存储单元之间，并且沿着第一方向布置成与第一格栅偏移的第二格栅。 第二隔热板沿着第二方向位于相邻存储单元之间，并沿着第一方向延伸的线排列。 一些实施例包括用于形成存储器阵列的方法。

    PULSE BASED MULTI-LEVEL CELL PROGRAMMING
    50.
    发明公开
    PULSE BASED MULTI-LEVEL CELL PROGRAMMING 审中-公开

    公开(公告)号：US20240347081A1

    公开(公告)日：2024-10-17

    申请号：US18633362

    申请日：2024-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C7/10 ,  G11C16/34

    CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/3404

    Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

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