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    ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE
    43.
    发明公开
    ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE 审中-公开

    公开(公告)号：US20230393776A1

    公开(公告)日：2023-12-07

    申请号：US17830625

    申请日：2022-06-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhenming Zhou ,  Murong Lang ,  Ching-Huang Lu ,  Nagendra Prasad Ganesh Rao

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0652

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

    Adjusting read-level thresholds based on write-to-write delay
    47.
    发明授权
    Adjusting read-level thresholds based on write-to-write delay 有权

    公开(公告)号：US11742029B2

    公开(公告)日：2023-08-29

    申请号：US17402279

    申请日：2021-08-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

    CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

    Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

    MANAGING A HYBRID ERROR RECOVERY PROCESS IN A MEMORY SUB-SYSTEM
    50.
    发明申请
    MANAGING A HYBRID ERROR RECOVERY PROCESS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20230069559A1

    公开(公告)日：2023-03-02

    申请号：US17462605

    申请日：2021-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

    IPC: G06F3/06

    Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

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