公开(公告)号：US20210343640A1

公开(公告)日：2021-11-04

申请号：US17374634

申请日：2021-07-13

Applicant: Micron Technology, Inc.

Inventor： Vladimir Machkaoutsan ,  Pieter Blomme ,  Emilio Camerlenghi ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer ,  Paolo Tessariol

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/311

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. First dummy pillars in the memory blocks extend through at least a majority of the insulative tiers and the conductive tiers through which the channel-material strings extend. Second dummy pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The second dummy pillars extend through at least a majority of the insulative tiers and the conductive tiers through which the operative channel-material strings extend laterally-between the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US11158673B2

公开(公告)日：2021-10-26

申请号：US16771658

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Paolo Tessariol

IPC: G11C16/04 ,  H01L27/24 ,  G11C8/08

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

公开(公告)号：US11087991B2

公开(公告)日：2021-08-10

申请号：US16514928

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Eric Freeman ,  Paolo Tessariol

IPC: H01L21/311 ,  H01L49/02 ,  H01L23/522 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

公开(公告)号：US20210233591A1

公开(公告)日：2021-07-29

申请号：US17228807

申请日：2021-04-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

公开(公告)号：US20210217730A1

公开(公告)日：2021-07-15

申请号：US16742485

申请日：2020-01-14

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/482 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US11056383B2

公开(公告)日：2021-07-06

申请号：US15881539

申请日：2018-01-26

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L27/115 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L27/11521

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US20210057439A1

公开(公告)日：2021-02-25

申请号：US16550244

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Jian Li ,  Ryan L. Meyer

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks. The pillars are directly against conducting material of conductive lines in the conductive tiers. Other arrays, and methods, are disclosed.

公开(公告)号：US10756105B2

公开(公告)日：2020-08-25

申请号：US16200158

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  M. Jared Barclay ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28

Abstract: A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.

公开(公告)号：US20190259703A1

公开(公告)日：2019-08-22

申请号：US16405184

申请日：2019-05-07

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L27/11575 ,  H01L21/768 ,  H01L23/522

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20190229127A1

公开(公告)日：2019-07-25

申请号：US16372563

申请日：2019-04-02

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Matthew Park ,  Joseph Neil Greeley ,  Chet E. Carter ,  Martin C. Roberts ,  Indra V. Chary ,  Vinayak Shamanna ,  Ryan Meyer ,  Paolo Tessariol

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.