公开(公告)号：US20230195656A1

公开(公告)日：2023-06-22

申请号：US17556908

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  Nikesh Agarwal

IPC: G06F13/16 ,  G06F9/30

CPC classification number: G06F13/1621 ,  G06F13/1642 ,  G06F13/1668 ,  G06F9/30043 ,  G06F9/30101

Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to control the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request across an interconnect responsive to possession of a credit. If the transmitter exhausts its credits, the transmitter waits until a credit is returned before transmitting another request. The receiver can manage credit returns based on how many responses are present in a response queue. The receiver can change a rate at which the credit returns are transmitted by changing a size of an interval of responses that are being transmitted, with one credit being returned per interval. This can slow the rate of credit returns while the response queue is relatively more filled. The rate adjustment can decrease latency by reducing an amount of requests or responses that are pooling in backend components.

公开(公告)号：US20230195368A1

公开(公告)日：2023-06-22

申请号：US17558465

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Nikesh Agarwal ,  Laurent Isenegger ,  Robert Walker

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0238

Abstract: Described apparatuses and methods relate to a write request buffer for a memory system that may support a nondeterministic protocol. A host device and connected memory device may include a controller with a read queue and a write queue. A controller includes a write request buffer to buffer write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores most-recent write data associated with the unique write addresses. Incoming read requests are compared with the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to backend memory. Accordingly, the write request buffer can improve the latency and bandwidth in accessing a memory device over an interconnect.

公开(公告)号：US11372763B2

公开(公告)日：2022-06-28

申请号：US16928766

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Ashay Narsale ,  Robert Walker

IPC: G06F12/0862 ,  G06F13/42 ,  G06F13/16

Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.

公开(公告)号：US11119908B2

公开(公告)日：2021-09-14

申请号：US16886252

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F1/20 ,  G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G11C7/04 ,  G06F1/3234 ,  G06F9/50 ,  G06F12/122 ,  G06F13/24 ,  G06F13/42 ,  G11C11/406

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

公开(公告)号：US20210157510A1

公开(公告)日：2021-05-27

申请号：US16694427

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Robert Walker

IPC: G06F3/06

Abstract: Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.

公开(公告)号：US20210081338A1

公开(公告)日：2021-03-18

申请号：US17099309

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F13/16

Abstract: Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.

公开(公告)号：US10817412B2

公开(公告)日：2020-10-27

申请号：US16030600

申请日：2018-07-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory configured to store information. Memory of the memory is configured with two or more information depth maps. The example apparatus further includes a memory translation unit (MTU) configured to support an intermediate depth map of the memory during the migration of the information stored at the memory from a first information depth map of the two or more information depth maps to a second information depth map of the two or more information depth by maintaining mapping tables. The MTU is further configured to provide a mapped address associated with a requested address of a memory access request to the memory based on the mapping tables.

公开(公告)号：US20200065027A1

公开(公告)日：2020-02-27

申请号：US16111974

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US09933972B2

公开(公告)日：2018-04-03

申请号：US14542750

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F12/10 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/06 ,  G06F12/0653 ,  Y02D10/13

Abstract: Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.

公开(公告)号：US20160259721A1

公开(公告)日：2016-09-08

申请号：US15156022

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F12/02 ,  G06F13/16 ,  G06F13/42 ,  G06F3/06

CPC classification number: G06F12/0223 ,  G06F1/206 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/122 ,  G06F13/1668 ,  G06F13/24 ,  G06F13/4282 ,  G06F2212/1016 ,  G11C7/04 ,  G11C11/40626 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/16

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

Abstract translation: 描述了将存储区域映射到基于存储器区域的热数据的处理的方法。 在一些实施例中，存储器控制器可以接收存储器分配请求。 存储器分配请求可以包括逻辑存储器地址。 该方法还可以包括基于存储器系统的存储器区域的热数据将逻辑存储器地址映射到存储器系统的存储器区域中的地址。 还描述了附加的方法和系统。