公开(公告)号：US11810607B2

公开(公告)日：2023-11-07

申请号：US17185488

申请日：2021-02-25

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56 ,  H10B53/00 ,  H10B53/20

CPC classification number: G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/5657 ,  H10B53/00 ,  H10B53/20

Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

公开(公告)号：US11798634B2

公开(公告)日：2023-10-24

申请号：US17675622

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32 ,  G11C11/4074 ,  G11C11/417

CPC classification number: G11C16/30 ,  G11C5/144 ,  G11C5/147 ,  G11C7/20 ,  G11C11/4074 ,  G11C11/417 ,  G11C16/045 ,  G11C16/12 ,  G11C16/32

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

公开(公告)号：US11721372B2

公开(公告)日：2023-08-08

申请号：US17895565

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara ,  Yusuke Jono ,  Donald Martin Morgan ,  Nobuo Yamamoto

IPC: G11C7/20 ,  G11C11/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/18

CPC classification number: G11C7/065 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：US11176985B1

公开(公告)日：2021-11-16

申请号：US16925057

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Hiroshi Akamatsu ,  Takamasa Suzuki ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/30 ,  G11C5/14

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

公开(公告)号：US20210350861A1

公开(公告)日：2021-11-11

申请号：US16870670

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

IPC: G11C16/30 ,  G11C16/12 ,  G11C16/32 ,  G11C16/04 ,  G11C7/20

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

公开(公告)号：US20210210129A1

公开(公告)日：2021-07-08

申请号：US17103521

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G11C11/4091 ,  G06F12/14 ,  G11C8/08

Abstract: Methods, systems, and devices for protecting stored data in a memory device are described. In one example, a memory device may include a set of memory cells coupled with a digit line and a plate line. A method of operating the memory device may include performing an access operation on a selected memory cell of the set of memory cells, and performing an equalization operation on a non-selected memory cell of the plurality of memory cells based on performing the access operation. The equalization operation may include applying an equal voltage to opposite terminals of the non-selected memory cell via the digit line and the plate line, which may allow built-up charge, such as leakage charge resulting from the access operation, to dissipate. Such an equalization operation may reduce a likelihood of memory loss in non-selected memory cells after access operations.

公开(公告)号：US20200335147A1

公开(公告)日：2020-10-22

申请号：US16869510

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US10553594B2

公开(公告)日：2020-02-04

申请号：US16138256

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasushi Matsubara

IPC: G11C11/22 ,  H01L27/11502 ,  H01L27/10 ,  H01L49/02 ,  G11C5/14

Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.

公开(公告)号：US10373921B2

公开(公告)日：2019-08-06

申请号：US15628343

申请日：2017-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasushi Matsubara

IPC: H01L23/02 ,  H01L23/64 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H02M7/00 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4072 ,  G11C11/408

Abstract: Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.

公开(公告)号：US20190066751A1

公开(公告)日：2019-02-28

申请号：US16050141

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56 ,  H01L27/11502

CPC classification number: G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/5657 ,  H01L27/11502 ,  H01L27/11514

Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.