公开(公告)号：US20170373075A1

公开(公告)日：2017-12-28

申请号：US15685878

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1158 ,  H01L21/822 ,  H01L27/11529 ,  H01L27/11578

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US20170317098A1

公开(公告)日：2017-11-02

申请号：US15651719

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76 ,  H01L29/7827

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20170054036A1

公开(公告)日：2017-02-23

申请号：US14830517

申请日：2015-08-19

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H01L29/792 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L29/66666 ,  H01L29/76

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract translation: 一些实施例包括具有导电材料的集成结构，导电材料上的选择器件栅极材料以及选择器件栅极材料上的垂直堆叠的导电电平。 垂直延伸的单片通道材料与选择器件栅极材料和导电电平相邻。 单片通道材料包含与选择器件栅极材料相邻的下部段和邻近导电层的上段。 第一垂直延伸区域在单片通道材料的下段和选择器件栅极材料之间。 第一垂直延伸区域包含第一材料。 第二垂直延伸区域位于单片通道材料的上部段和导电层之间。 第二垂直延伸区域包含与第一材料的组成不同的材料。

公开(公告)号：US20160172373A1

公开(公告)日：2016-06-16

申请号：US15049097

申请日：2016-02-21

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

公开(公告)号：US09287379B2

公开(公告)日：2016-03-15

申请号：US14281569

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/115 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

公开(公告)号：US20250142827A1

公开(公告)日：2025-05-01

申请号：US19009758

申请日：2025-01-03

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H10B43/27 ,  H10D30/01 ,  H10D30/63 ,  H10D48/36

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US11653494B2

公开(公告)日：2023-05-16

申请号：US16725139

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat ,  Luan C. Tran ,  Meng-Wei Kuo ,  Yushi Hu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/1158

CPC classification number: H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/8221 ,  H01L27/1158 ,  H01L27/11529 ,  H01L27/11578

Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.

公开(公告)号：US20220238543A1

公开(公告)日：2022-07-28

申请号：US17723716

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

IPC: H01L27/11556 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

公开(公告)号：US10731273B2

公开(公告)日：2020-08-04

申请号：US16436501

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： John Mark Meldrim ,  Yushi Hu ,  Yongjun Jeff Hu ,  Everett Allen McTeer

IPC: C30B29/38 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11582 ,  C30B23/02 ,  C30B25/02 ,  H01L21/225 ,  H01L27/11524 ,  H01L27/1157

Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.

公开(公告)号：US10658382B2

公开(公告)日：2020-05-19

申请号：US16386544

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock ,  Yushi Hu ,  Christopher Larsen ,  Dimitrios Pavlopoulos

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/532 ,  H01L23/528

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.