公开(公告)号：US20210182189A1

公开(公告)日：2021-06-17

申请号：US16076288

申请日：2017-12-11

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo laculo

IPC: G06F12/02 ,  G06F12/1009

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11023167B2

公开(公告)日：2021-06-01

申请号：US16136101

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US20190018618A1

公开(公告)日：2019-01-17

申请号：US16136101

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

IPC: G06F3/06 ,  G06F12/00

Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

公开(公告)号：US12183407B2

公开(公告)日：2024-12-31

申请号：US17736902

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Tao Liu ,  Ting Luo ,  Dionisio Minopoli ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari ,  Walter Di Francesco ,  Antonino Pollio ,  Luigi Esposito ,  Anna Scalesse ,  Allison J. Olson ,  Anna Chiara Siviero

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for setting switching for single-level cells (SLCs) are described. A memory system may receive an access command from a host. The access command may correspond to an SLC block or to a multiple-level cell block. If the access command corresponds to an SLC block, the memory system may modify the access command to include one or more bits indicating a setting to use for performing the access operation corresponding to the access command. The setting may define one or more operating parameters for performing the access operation. The memory system may use bits to indicate the setting that are used to indicate a page address for multiple-level cell blocks. The memory system may issue the access command to a memory device, which may perform the access operation using the setting indicated in the one or more bits included by the memory system.

公开(公告)号：US12073113B2

公开(公告)日：2024-08-27

申请号：US17461469

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Lalla Fatima Drissi ,  Doriana Tardio ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

公开(公告)号：US11907556B2

公开(公告)日：2024-02-20

申请号：US17580296

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Luigi Esposito ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara ,  Carminantonio Manganelli ,  Salvatore Del Prete

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F12/0246 ,  G06F12/0646 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/7205

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

公开(公告)号：US20230367478A1

公开(公告)日：2023-11-16

申请号：US18137820

申请日：2023-04-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Carminantonio Manganelli ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0679 ,  G06F3/0655

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

公开(公告)号：US11650931B2

公开(公告)日：2023-05-16

申请号：US17234062

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/7201

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

公开(公告)号：US20230111015A1

公开(公告)日：2023-04-13

申请号：US17971414

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luca Porzio ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

公开(公告)号：US20220414003A1

公开(公告)日：2022-12-29

申请号：US17902384

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

IPC: G06F12/02 ,  G06F12/1009

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.