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    Semiconductor integrated circuit device and method of manufacturing the same
    41.
    发明申请
    Semiconductor integrated circuit device and method of manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US20060113520A1

    公开(公告)日：2006-06-01

    申请号：US11289410

    申请日：2005-11-30

    申请人： Naoki Yamamoto ,  Norikatsu Takaura ,  Yuichi Matsui ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Motoyasu Terao

    发明人： Naoki Yamamoto ,  Norikatsu Takaura ,  Yuichi Matsui ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Motoyasu Terao

    IPC分类号： H01L29/04

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

    摘要： Disclosed herein is a phase change memory semiconductor integrated circuit device using a chalcogenide film that solves a problem that the operation temperature capable of ensuring long time memory retention is low due to low phase change temperature is and, at the same time, a problem that power consumption of the device is high since a large current requires to rewrite memory information due to low resistance. A portion of constituent elements for a chalcogenide comprises nitride, oxide or carbide which are formed to the boundary between the chalcogenide film and a metal plug as an underlying electrode and to the grain boundary of chalcogenide crystals thereby increasing the phase change temperature and high Joule heat can be generated even by a small current by increasing the resistance of the film.

    摘要翻译： 这里公开了一种使用硫族化物膜的相变存储器半导体集成电路器件，其解决了由于相变温度低导致能够确保长时间存储保持的操作温度低的问题，并且同时存在功率 器件的消耗很高，因为大电流需要由于低电阻而重写存储器信息。 硫族化物的一部分组成元素包括氮化物，氧化物或碳化物，其形成于作为下伏电极的硫族化物膜和金属栓之间的边界以及硫族化物晶体的晶界上，从而增加相变温度和高焦耳热 即使通过增加膜的电阻也能通过小的电流产生。

    SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME
    43.
    发明申请
    SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100171087A1

    公开(公告)日：2010-07-08

    申请号：US12600333

    申请日：2007-05-21

    申请人： Kenzo Kurotsuchi ,  Motoyasu Terao ,  Takahiro Morikawa ,  Norikatsu Takaura

    发明人： Kenzo Kurotsuchi ,  Motoyasu Terao ,  Takahiro Morikawa ,  Norikatsu Takaura

    IPC分类号： H01L45/00 ,  H01L21/06

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： In a semiconductor device including a phase change memory element whose memory layer is formed of a phase change material of M (additive element)-Ge (germanium)-Sb (antimony)-Te (tellurium), both of high heat resistance and stable data retention property are achieved. The memory layer has a fine structure with a different composition ratio therein, and an average composition of MαGeXSbYTeZ forming the memory layer satisfies the relations of 0≦α≦0.4, 0.04≦X≦0.4, 0≦Y≦0.3, 0.3≦Z≦0.6, and 0.03≦(α+Y).

    摘要翻译： 在包括由M（添加元素）-Ge（锗）-Sb（锑）-Te（碲）的相变材料形成的存储层的相变存储元件的半导体器件中，高耐热性和稳定数据 保留性能得以实现。 存储层具有不同组成比的精细结构，形成记忆层的MαGeXSbYTeZ的平均组成满足0＆lt; nlE;α＆nlE; 0.4,0.04＆nlE; X＆lt; lE; 0.4,0＆amp; nlE; Y＆nlE; 0.3,0.3＆ Z＆NlE; 0.6和0.03＆nlE;（α+ Y）。

    SEMICONDUCTOR DEVIC
    44.
    发明申请
    SEMICONDUCTOR DEVIC 失效
    半导体器件

    公开(公告)号：US20100012917A1

    公开(公告)日：2010-01-21

    申请号：US12302740

    申请日：2006-05-31

    申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    IPC分类号： H01L47/00

    CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

    摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

    Semiconductor device
    46.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08513640B2

    公开(公告)日：2013-08-20

    申请号：US12094403

    申请日：2006-11-14

    申请人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    发明人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi

    IPC分类号： H01L29/06 ,  H01L21/00

    CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

    摘要翻译： 在相同的半导体衬底1上，存储单元阵列，其中具有存储具有高电阻值的高电阻状态的硫族化物材料存储层22的多个存储元件R和具有低电阻的低电阻状态 在存储单元区域mmry中形成以矩阵形式设置的原子排列变化的值，在逻辑电路区域lgc中形成半导体集成电路。 该硫属化物材料储存层22由含有10.5原子％以上至40原子％以下的Ga或In中的至少任一种的硫属元素化物构成，5原子％以上且35原子％以下的Ge，Sb 为5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。

    Semiconductor device and method of manufacturing the same
    49.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20060105556A1

    公开(公告)日：2006-05-18

    申请号：US11272811

    申请日：2005-11-15

    申请人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    发明人： Yuichi Matsui ,  Motoyasu Terao ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Naoki Yamamoto

    IPC分类号： H01L21/20

    CPC分类号： C23C14/5806 ,  C23C14/0623 ,  C23C14/541 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

    摘要： The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

    摘要翻译： 在相变存储器的布线处理所需的400℃以上所需的退火处理的问题在于，硫属化物材料中的晶粒沿倾斜方向生长，从而在储存层中产生空隙。 这些空隙又由于粘合力的降低而导致剥离，由于与插头的不正确接触导致的电阻变化以及其它不期望的事件。 在非晶态形成硫族化物材料之后，进行后退火以形成（111）取向和柱状结构的面心立方。 此后进一步进行高温退火以形成柱状，六边形最接近填充的晶体。 使用该方法可以抑制由于在垂直于相关衬底的表面的方向上形成晶粒而导致空隙的倾斜晶粒的生长。

    SEMICONDUCTOR STORAGE DEVICE
    50.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 失效
    半导体存储设备

    公开(公告)号：US20100061132A1

    公开(公告)日：2010-03-11

    申请号：US12516690

    申请日：2006-12-07

    申请人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

    发明人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

    IPC分类号： G11C11/00 ,  H01L45/00 ,  G11C5/02 ,  G11C7/00

    CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233

    摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.

    摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。