公开(公告)号：US20050097302A1

公开(公告)日：2005-05-05

申请号：US10967579

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/14 ,  G06F15/16 ,  G06F15/80 ,  G06F21/24 ,  H04L29/06 ,  G06F15/00

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system is provided for processing programs and data. The processing system has a processing unit and multiple sub-processing units. Each sub-processing unit includes a dedicated local memory for storing programs and data. The dedicated local memory of each respective sub-processing unit is not a cache memory. In an alternative, multiple computing devices may connect to one another via a communications network, and each computing device may include at least one processing element having the processing unit and sub-processing units.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 提供处理程序和数据的处理系统。 处理系统具有处理单元和多个子处理单元。 每个子处理单元包括用于存储程序和数据的专用本地存储器。 各个子处理单元的专用本地存储器不是高速缓冲存储器。 替代地，多个计算设备可以经由通信网络彼此连接，并且每个计算设备可以包括具有处理单元和子处理单元的至少一个处理单元。

公开(公告)号：US20050055505A1

公开(公告)日：2005-03-10

申请号：US10655365

申请日：2003-09-04

申请人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Day ,  Harm Hofstee ,  Charles Johns ,  James Kahle ,  David Shippy ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/126

摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

公开(公告)号：US20050055478A1

公开(公告)日：2005-03-10

申请号：US10655370

申请日：2003-09-04

申请人： Charles Johns ,  Peichun Liu ,  Thuong Truong ,  Asano Shigehiro ,  Takeshi Yamazaki

发明人： Charles Johns ,  Peichun Liu ,  Thuong Truong ,  Asano Shigehiro ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

摘要翻译： 提供了一种用于为第一处理器建立直接存储器访问的系统和方法。 该系统包括第一处理器和本地存储器。 本地存储器耦合到第一处理器。 第一直接存储器存取控制器（DMAC）耦合到第一处理器和本地存储器。 系统存储器与第一DMAC通信。 第二处理器与第一DMAC通信，使得第二处理器设置第一DMAC来处理本地存储器和系统存储器之间的数据传输。 当第一个DMAC完成处理数据传输时，第二个处理器中断。

公开(公告)号：US06826662B2

公开(公告)日：2004-11-30

申请号：US09815554

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1200

CPC分类号： G06F12/0815 ,  G06F9/544 ,  G06F21/79 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US06809734B2

公开(公告)日：2004-10-26

申请号：US09815558

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

IPC分类号： G06T120

CPC分类号： G06F9/4893 ,  A63F2300/20 ,  A63F2300/538 ,  Y02D10/24

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US06779049B2

公开(公告)日：2004-08-17

申请号：US09736585

申请日：2000-12-14

申请人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1328

CPC分类号： G06F12/1027 ,  G06F2212/682

摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

摘要翻译： 用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。 在一个实施例中，系统包括共享存储器。 该系统还包括耦合到共享存储器的多个处理元件。 多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。 每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。 每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。 相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

公开(公告)号：US06720713B2

公开(公告)日：2004-04-13

申请号：US09861733

申请日：2001-05-21

申请人： Shigemasa Kusabiraki ,  Takeshi Yamazaki ,  Yuji Kosugi

发明人： Shigemasa Kusabiraki ,  Takeshi Yamazaki ,  Yuji Kosugi

IPC分类号： H01L4108

CPC分类号： H03H9/178 ,  H03H9/0514 ,  H03H9/1014

摘要： While suppressing that a vibration of a piezo-electric element propagates to a substrate by devising the composition of an electro-conductive support body, the piezoelectric resonant component which secures electroconductivity and can maintain a fall-proof shock property is provided. The piezoelectric resonant component has a substrate 20 on the top surface of which pattern electrodes 21 and 22 are formed, and on the lower surface of which it has electrodes 8 and 9. It has a piezoelectric element 1 using the length vibration on the substrate 20. Electro-conductive support bodies 10 and 11 are fixed to the length direction center section of the lower surface electrodes of the piezoelectric element 1. The connection fixation of these support bodies 10 and 11 to the pattern electrodes 21 and 22 of the substrate 20 is performed by electro-conductive adhesives 12 and 13. The electro-conductive support bodies 10 and 11 include an urethane resin which contains an electro-conductive filler, making the rate of content of the electro-conductive filler 75-85 wt %.

摘要翻译： 通过设计导电性支撑体的组成来抑制压电元件的振动抑制振动，能够提供确保导电性且能够保持防摔冲击性的压电谐振部件。 压电谐振元件在其表面上形成有图案电极21和22的基板20，其下表面具有电极8和9.它具有使用基板20上的长度振动的压电元件1 导电性支撑体10,11固定在压电元件1的下表面电极的长度方向中央部。这些支撑体10,11与基板20的图案电极21,22的连接固定为 由导电粘合剂12和13执行。导电支撑体10和11包括含有导电填料的聚氨酯树脂，使导电填料的含量为75-85wt％。

公开(公告)号：US06526491B2

公开(公告)日：2003-02-25

申请号：US09816020

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1202

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

公开(公告)号：US06385838B1

公开(公告)日：2002-05-14

申请号：US09464089

申请日：1999-12-16

申请人： Takeshi Yamazaki ,  Syunji Kumamoto ,  Fumio Yuito

发明人： Takeshi Yamazaki ,  Syunji Kumamoto ,  Fumio Yuito

IPC分类号： B23Q1700

CPC分类号： G03B17/26 ,  Y10T29/49771 ,  Y10T29/4978 ,  Y10T29/53052 ,  Y10T29/53061 ,  Y10T29/53465

摘要： To manufacture a film unit, a filmstrip is advanced out of a cartridge shell by rotating a spool of the cartridge shell through a spool drive shaft. The spool drive shaft stops when the filmstrip is advanced a predetermined length out of the cartridge shell. A rotational position of the spool at the stop of the spool drive shaft is detected based on a rotational position of the spool drive shaft. The cartridge shell is disengaged from the spool drive shaft while the rotational position of the spool and the advanced length of the filmstrip are maintained unchanged. The spool of the cartridge shell is engaged with a film supply shaft, after adjusting a rotational position of the film supply shaft to the rotational position of the spool, while the leading end of the filmstrip is secured to a winding shaft. The filmstrip is wound into a roll by rotating the winding shaft.

摘要翻译： 为了制造胶卷单元，通过使卷筒驱动轴旋转盒壳的卷轴，将胶卷从盒壳推出。 当胶卷从墨盒外壳推进预定长度时，卷轴驱动轴停止。 基于卷轴驱动轴的旋转位置检测卷轴驱动轴的停止处的卷轴的旋转位置。 当卷轴的旋转位置和胶片的前进长度保持不变时，盒壳与卷轴驱动轴脱离。 在将胶片供应轴的旋转位置调节到卷轴的旋转位置之后，墨盒外壳的卷轴与胶片供应轴接合，同时胶片的前端固定到卷轴上。 通过旋转卷轴将胶片卷成卷。

公开(公告)号：US06285279B1

公开(公告)日：2001-09-04

申请号：US09325342

申请日：1999-06-04

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： B62J300

CPC分类号： B60K26/021 ,  B60W2530/00 ,  B60W2550/20 ,  B60W2550/308 ,  B60Y2200/12

摘要： To provide an information device that makes it possible to easily reduce the overall reaction time and makes it difficult to overlook a warning. An information device includes an external force generator for supplying external force to an operator touched by the extremities, the hands or feet, of a driver at the time of operation of the vehicle. A judging member is provided for receiving an external signal and judging traffic conditions. A control member controls the driving of the external force generator based on the judgement result of the judging member.

摘要翻译： 提供一种使得可以容易地减少总体反应时间并使得难以忽视警告的信息装置。 信息装置包括外部力发生器，用于在车辆操作时向驾驶员的四肢，手或脚触及的操作者提供外力。 提供一个用于接收外部信号并判断交通状况的判断成员。 控制部件根据判断部件的判定结果来控制外力生成部的驱动。