公开(公告)号：US20190272881A1

公开(公告)日：2019-09-05

申请号：US16416177

申请日：2019-05-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Jung Sheng Hoei ,  Michael G. Miller ,  Roland J. Awusie ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Gary F. Besinga ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G11C16/34

Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

公开(公告)号：US20190267105A1

公开(公告)日：2019-08-29

申请号：US16412879

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US10331553B2

公开(公告)日：2019-06-25

申请号：US15478631

申请日：2017-04-04

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Daniel J. Hubbard ,  Renato C. Padilla ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G06F3/06 ,  G06F12/02

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

公开(公告)号：US20190130983A1

公开(公告)日：2019-05-02

申请号：US15799655

申请日：2017-10-31

Applicant: Micron Technology, Inc.

Inventor： Harish Singidi ,  Scott Stoller ,  Jung Sheng Hoei ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Kishore Kumar Muchherla

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/04

Abstract: NAND memory devices, are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.

公开(公告)号：US20190122705A1

公开(公告)日：2019-04-25

申请号：US16230251

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish Reddy Singidi ,  Gianni Stephen Alsasua ,  Gary F. Besinga ,  Sampath Ratnam ,  Peter Sean Feeley

IPC: G11C7/10 ,  G11C8/10

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190073251A1

公开(公告)日：2019-03-07

申请号：US16178963

申请日：2018-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Violante Moschiano ,  Peter Feeley ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Walter Di-Francesco ,  Renato C. Padilla, JR. ,  Yun Li ,  Kishore Kumar Muchherla

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/073 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F11/1068 ,  G11C5/144 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C16/30 ,  G11C16/3459

Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.

公开(公告)号：US20180293003A1

公开(公告)日：2018-10-11

申请号：US15482337

申请日：2017-04-07

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Preston A. Thomson ,  Renato C. Padilla ,  Ashutosh Malshe

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US20180285258A1

公开(公告)日：2018-10-04

申请号：US15478631

申请日：2017-04-04

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Daniel J. Hubbard ,  Renato C. Padilla ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0253 ,  G06F3/061 ,  G06F12/0246 ,  G06F2212/7205

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

公开(公告)号：US20240192878A1

公开(公告)日：2024-06-13

申请号：US18584814

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Antonio D. Bianco

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/7211

Abstract: A method includes determining a health characteristic value of a block of memory cells, determining a difference between the health characteristic value and a health threshold, determining, based on the difference, a weight to associate with a block of memory cells, selecting, based on the weight, a block of memory cells for a media management operation; and performing a media management operation on the selected block of memory cells.

公开(公告)号：US12009042B2

公开(公告)日：2024-06-11

申请号：US17980234

申请日：2022-11-03

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Gianni S. Alsasua ,  Harish R. Singidi

IPC: G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0882 ,  G11C29/10 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0882 ,  G11C29/10 ,  G11C29/44

Abstract: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.