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公开(公告)号：US20180284820A1
公开(公告)日：2018-10-04
申请号：US16000220
申请日：2018-06-05
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
Abstract: An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap transistor coupled to the output of the amplifier at a control electrode thereof, the bandgap transistor being further coupled commonly to the first and second inputs of the amplifier at a first electrode thereof to form a feedback path. The apparatus further comprises a resistor coupled to the first electrode of the bandgap transistor.
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42.发明申请公开(公告)号：US20180095486A1
公开(公告)日：2018-04-05
申请号：US15283605
申请日：2016-10-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yuanzhong Wan , Dong Pan
Abstract: Systems and apparatuses for a configurable, temperature dependent reference voltage generator are provided. An example apparatus includes control logic configured receive temperature data, and produce a signal, based on the temperature data, indicative of the temperature data, a temperature dependence and a temperature slope. The apparatus may also include a temperature slope reference generator configured to produce a reference voltage having the temperature dependence and the temperature slope, based on the signal from the control logic.
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43.发明申请公开(公告)号：US20170288542A1
公开(公告)日：2017-10-05
申请号：US15087271
申请日：2016-03-31
Applicant: Micron Technology, Inc.
Inventor： Yuanzhong Wan , Dong Pan
Abstract: According to one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a voltage regulator configured to produce a regulated voltage, a plurality of current circuits coupled in parallel between an output node and a power node, each of the plurality of current circuits including first and second transistors coupled in series, the first transistor of each of the plurality of current circuits being biased with the regulated voltage, and a control circuit configured to activate the second transistor of selected one or ones of the plurality of current circuits responsive, at least in part, to a voltage at the output node.
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公开(公告)号：US09671294B2
公开(公告)日：2017-06-06
申请号：US14887138
申请日：2015-10-19
Applicant: Micron Technology, Inc.
Inventor： Dong Pan
Abstract: A semiconductor device including a temperature sensor includes a pull up circuit, a pull down circuit, a first additional current path, and a second additional current path. The pull up circuit is configured to generate a pull up current that contributes to generation of a first output current. The pull down circuit is operably coupled to the pull up circuit at an output node and configured to generate a pull down current that contributes to generation of a second output current. The first additional current path, when enabled, is configured to combine a first additional current with the pull up current to comprise the first output current. The second additional current path, when enabled, is configured to combine a second additional current with the pull down current to comprise the second output current. Respective enablement of the first additional current path and the second additional current path is complementary.
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公开(公告)号：US09306518B2
公开(公告)日：2016-04-05
申请号：US14287381
申请日：2014-05-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan
IPC: G11C5/14 , H03F3/45 , G11C7/12 , G11C7/06 , G11C11/4091 , G11C11/4097
CPC classification number: H03F3/45071 , G11C5/147 , G11C7/06 , G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4097 , H03F3/45183 , H03F2203/45264
Abstract: Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit my allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided.
Abstract translation: 提供了电路，装置和方法，例如放大器（例如，电压调节器），其包括通过反馈路径提供负反馈的反馈电路。 一个这样的反馈路径包括与“单向”隔离电路串联耦合的电容，通过该电路耦合反馈信号。 “单向”隔离电路允许反馈信号从诸如输出节点的“下游”节点耦合到“上游”节点，例如产生错误信号以产生负值的节点 反馈。 然而，“单向”隔离电路可以基本上防止上游节点处的电压变化与隔离电路中的电容耦合。 结果，可以避免上游节点处的电压响应于上游节点处的电压变化而对电容进行充电和放电，所以上游节点处的电压可能快速变化。
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Patent Agency Ranking
公开(公告)号：US09246382B2
公开(公告)日：2016-01-26
申请号：US13962596
申请日：2013-08-08
Applicant: Micron Technology, Inc.
Inventor： Dong Pan , John F. Schreck
IPC: H02M3/07
CPC classification number: H02M3/07
Abstract: Some embodiments include apparatuses and methods having an input node to receive a first voltage, an output node to provide an output voltage, and a charge pump to generate the output voltage based on the first voltage. The charge pump can include a control node to receive a control signal for controlling at least one switch of the charge pump, such that the output voltage includes a value greater than a value of the first voltage. The control signal can include a level corresponding to a second voltage having a value greater than the value of the output voltage. Additional apparatus and methods are described.
Abstract translation: 一些实施例包括具有用于接收第一电压的输入节点，提供输出电压的输出节点和电荷泵以根据第一电压产生输出电压的装置和方法。 电荷泵可以包括控制节点，以接收用于控制电荷泵的至少一个开关的控制信号，使得输出电压包括大于第一电压值的值。 控制信号可以包括对应于具有大于输出电压值的值的第二电压的电平。 描述附加的装置和方法。
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公开(公告)号：US12165687B2
公开(公告)日：2024-12-10
申请号：US17565119
申请日：2021-12-29
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/40 , G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4097 , G11C11/4099
Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.
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公开(公告)号：US12132451B2
公开(公告)日：2024-10-29
申请号：US17583018
申请日：2022-01-24
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: H03F1/30 , G11C11/4074 , H02M3/155 , H03F1/02 , H03F3/21
CPC classification number: H03F1/301 , G11C11/4074 , H02M3/155 , H03F1/0233 , H03F3/211 , H03F2200/504
Abstract: Systems and devices are provided for tracking bandgap current generated by a bandgap circuit and mitigation of leakage current regardless of variations in PVT conditions. An apparatus may include one or more power amplifiers that powers components of the apparatus and comprising a transistor. The apparatus may also include bandgap current mirroring circuitry that generates a mirrored current that mirrors a received current that is process, voltage, and temperature (PVT) independent. The apparatus may also include a bulk voltage generator circuit including an amplifier having an input coupled to the bandgap current mirroring circuitry. Bulk voltage control circuitry is coupled to an output of the amplifier and generates a bulk voltage based on the relationship between the mirrored current and the leakage current.
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公开(公告)号：US11929749B2
公开(公告)日：2024-03-12
申请号：US17813291
申请日：2022-07-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhiqi Huang , Weilu Chu , Dong Pan
IPC: H03K5/134 , G11C11/4076 , G11C11/4093
CPC classification number: H03K5/134 , G11C11/4076 , G11C11/4093
Abstract: Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.
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公开(公告)号：US11824441B2
公开(公告)日：2023-11-21
申请号：US17840434
申请日：2022-06-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dong Pan , Beau D. Barry , Liang Liu
CPC classification number: H02M3/07 , G11C5/145 , G11C17/18 , H03K19/20 , G11C11/4074
Abstract: A multi-mode voltage pump may be configured to select an operational mode based on a temperature of a semiconductor device. The selected mode for a range of temperature values may be determined based on process variations and operational differences caused by temperature changes. The different selected modes of operation of the multi-mode voltage pump may provide pumped voltage having different voltage magnitudes. For example, the multi-mode voltage pump may operate in a first mode that uses two stages to provide a first VPP voltage, a second mode that uses a single stage to provide a second VPP voltage, or a third mode that uses a mixture of a single stage and two stages to provide a third VPP voltage. The third VPP voltage may be between the first and second VPP voltages, with the first VPP voltage having the greatest magnitude. Control signal timing of circuitry of the multi-mode voltage pump may be based on an oscillator signal.
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