公开(公告)号：US11276454B2

公开(公告)日：2022-03-15

申请号：US16939669

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C16/34 ,  G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

公开(公告)号：US20210335394A1

公开(公告)日：2021-10-28

申请号：US17372329

申请日：2021-07-09

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  George B. Raad ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C5/14 ,  G11C7/22

Abstract: A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.

公开(公告)号：US11120860B1

公开(公告)日：2021-09-14

申请号：US16987168

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer

IPC: G11C11/40 ,  G11C11/406

Abstract: Methods of operating a number of memory devices are disclosed. A method may include adjusting a count of a refresh address counter of at least one memory device of a number of memory devices such that the count of the refresh address counter of the at least one memory device is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. The method may also include receiving, at each of the number of memory devices, a refresh command. Further, the method may include refreshing, at each of the number of memory devices, a row of memory cells indicated by the count of an associated refresh address counter. Related systems and memory modules are also described.

公开(公告)号：US20210264971A1

公开(公告)日：2021-08-26

申请号：US17315654

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C11/406 ,  G11C11/00 ,  G11C13/00 ,  G11C11/22 ,  G11C11/16

Abstract: Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US11069426B1

公开(公告)日：2021-07-20

申请号：US16796511

申请日：2020-02-20

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer ,  Seth A. Eichmeyer

IPC: G11C29/00 ,  G11C11/408 ,  G11C11/406

Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes a plurality of banks that each include (1) a plurality of memory cells and (2) a plurality of redundant cells configured to replace one or more target memory cells in the plurality of memory cells. A set of shared fuses and latches may be used to store a row address for each repair that may be implemented in one of the plurality of banks. A shared match circuit coupled to the set of shared latches and the plurality of memory banks may be configured to at least partially implement a row repair for the row address for a bank associated with a commanded operation.

公开(公告)号：US11017834B2

公开(公告)日：2021-05-25

申请号：US16205980

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  Sang-Kyun Park ,  Makoto Kitayama

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/22

Abstract: Methods, systems, and devices for refresh command management are described. A memory device may conduct a refresh operation to preserve the integrity of data stored to one or more memory cells. In some examples, the frequency of refresh operations conducted may be based on the memory device's temperature and may be initiated based on one or more commands received from an external device (e.g., a host device). Each command may be transmitted by the host device at a defined rate, which may impact the rate at which the memory device conducts one or more refresh operations. The memory device may postpone or skip at least a portion of one or more refresh operations based on one or more operating parameters of the memory device.

公开(公告)号：US20210098068A1

公开(公告)日：2021-04-01

申请号：US17119509

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/08 ,  G11C16/22 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

公开(公告)号：US20210064271A1

公开(公告)日：2021-03-04

申请号：US16553859

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Debra M. Bell ,  James S. Rehmeyer ,  Robert Bunnell ,  Nathaniel J. Meier

IPC: G06F3/06 ,  G11C17/16 ,  G11C17/18 ,  G11C11/4091 ,  G11C11/4072

Abstract: Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.

公开(公告)号：US20200211626A1

公开(公告)日：2020-07-02

申请号：US16237115

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4096 ,  G11C5/02 ,  H01L25/10 ,  G11C7/18

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US10606743B2

公开(公告)日：2020-03-31

申请号：US15831698

申请日：2017-12-05

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Timothy B. Cowles

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C7/24 ,  G11C7/06

Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.