公开(公告)号：US11747843B1

公开(公告)日：2023-09-05

申请号：US17717638

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Ekram H. Bhuiyan

IPC: G05F1/46 ,  G06F1/28 ,  G11C5/14

CPC classification number: G05F1/46 ,  G06F1/28 ,  G11C5/147

Abstract: Aspects of the present disclosure are directed to voltage drop compensation for power supplies. One method includes sensing each voltage, via a voltage sensor, of a plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor for at least one of the plurality of voltages, receiving, at a voltage manager, data for a number of characteristics of the circuitry components, and selecting a correction voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages and data for at least one of the characteristics of the circuitry components.

公开(公告)号：US11733274B1

公开(公告)日：2023-08-22

申请号：US17705819

申请日：2022-03-28

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Ekram H. Bhuiyan

IPC: G01R15/08 ,  G01R19/165 ,  G01R15/00

CPC classification number: G01R19/16557 ,  G01R15/005 ,  G01R15/08

Abstract: A voltage sensing circuit includes voltage regulators, oscillator circuits, delay circuits, and a detector circuit. The detector circuit detects characteristics of signaling received from a first oscillator circuit and characteristics of signaling received from a second oscillator circuit. The detector circuit compares the detected characteristics of the signaling from the first oscillator circuit and the second oscillator circuit to determine whether the detected characteristics from the first oscillator circuit and the second oscillator circuit meet a particular criterion for providing voltage manipulation for the voltage sensing circuit.

公开(公告)号：US12259812B2

公开(公告)日：2025-03-25

申请号：US17867375

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F12/02 ,  G06F9/50

Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.

公开(公告)号：US20250086056A1

公开(公告)日：2025-03-13

申请号：US18957253

申请日：2024-11-22

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Eyal En Gad ,  Fan Zhou

IPC: G06F11/10 ,  G06F7/501 ,  G06F11/07 ,  G11C29/44 ,  G11C29/52 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/37 ,  H03M13/45

Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

公开(公告)号：US20250069632A1

公开(公告)日：2025-02-27

申请号：US18787812

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G11C7/22 ,  G11C7/10

Abstract: An example method for critical timing driven adjustable voltage frequency scaling can include performing sensing operations on a system on chip (SoC) at a respective plurality of time windows each associated with a particular data value, comparing at least two of the particular data values associated with at least two respective time windows of the plurality of time windows, in response to the at least two of the particular data values being a same data value, determining that a clock margin is above a threshold clock margin, and determining that a clock margin is below a threshold clock margin. In some instance, in response to determining that the clock margin is above the threshold clock margin, a clocking of the SoC can be adjusted, a voltage of at least one operation of the SoC can be adjusted, and/or a clocking frequency of at least one operation of the SoC, among other possibilities.

公开(公告)号：US20240333305A1

公开(公告)日：2024-10-03

申请号：US18618082

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: H03M7/42 ,  H03M7/30

CPC classification number: H03M7/42 ,  H03M7/6005

Abstract: A method for initiator identifier compression includes associating respective initiator identifiers (IID) of a sub-set of initiators coupled via an interconnection structure to a target with respective parallel target data streams and performing, via an individual target data stream of the target data streams, an operation associated with the target and an individual initiator included in the sub-set of initiators.

公开(公告)号：US20240322675A1

公开(公告)日：2024-09-26

申请号：US18602819

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz

IPC: H02M3/04 ,  H03K3/037

CPC classification number: H02M3/04 ,  H03K3/037

Abstract: A method includes supplying, via a first voltage regulator, a first supply voltage to a first voltage domain including circuitry configured to operate at the first supply voltage, supplying, via a second voltage regulator, a second supply voltage to a second voltage domain including circuitry configured to operate in a voltage zone, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the second supply voltage to an altered supply voltage based on the change in the error characteristic.

公开(公告)号：US20240321380A1

公开(公告)日：2024-09-26

申请号：US18602782

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz

IPC: G11C29/50 ,  H03K3/037

CPC classification number: G11C29/50004 ,  H03K3/037 ,  G11C2029/5004

Abstract: A method includes supplying, via a voltage regulator, a supply voltage to a first voltage domain and a second voltage domain, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the supply voltage to an altered supply voltage based on the change in the error characteristic.

公开(公告)号：US20240272811A1

公开(公告)日：2024-08-15

申请号：US18431743

申请日：2024-02-02

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679

Abstract: A plurality of data entries are written in a first memory bank that comprises a portion of a data structure that is stored across a plurality of memory banks. For a subsequent data entry, a determination is made that the subsequent data entry has a value that is greater than a first data entry among the plurality of data entries in the first memory bank and less than a second data entry among the plurality of data entries in the first memory bank. The subsequent data entry is written to an address location in a second memory bank of the plurality of memory banks that is between a lowermost address location and an uppermost address location of the second memory bank and a first bit corresponding to the address location in the second memory bank to which the subsequent data entry was written is stored in the data structure.

公开(公告)号：US20240061485A1

公开(公告)日：2024-02-22

申请号：US17891331

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G06F1/28 ,  G11C5/14

CPC classification number: G06F1/28 ,  G11C5/147

Abstract: A method includes receiving signaling indicative of a temperature of a circuit portion area of a memory sub-system and receiving signaling indicative of a voltage or a current of the circuit portion area of the memory sub-system. The method further includes generating, based on the signaling indicative of temperature of the circuit portion area and the signaling indicative of the voltage or the current of the circuit portion area, a voltage management control signal and transferring the voltage management control signal to a voltage regulator of the memory sub-system. The method further includes operating the voltage regulator in response to receipt of the voltage management control signal to generate a voltage signal.