公开(公告)号：US11250918B2

公开(公告)日：2022-02-15

申请号：US17035149

申请日：2020-09-28

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

IPC分类号： G06F12/00 ,  G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

摘要： Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US20210287748A1

公开(公告)日：2021-09-16

申请号：US17331395

申请日：2021-05-26

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC分类号： G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

摘要： Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US20210241823A1

公开(公告)日：2021-08-05

申请号：US17238846

申请日：2021-04-23

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, JR.

IPC分类号： G11C11/406 ,  G06F13/16 ,  G11C7/04

摘要： Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US10998034B2

公开(公告)日：2021-05-04

申请号：US17017201

申请日：2020-09-10

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC分类号： G11C7/04 ,  G11C11/406 ,  G06F13/16

摘要： Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US10915395B2

公开(公告)日：2021-02-09

申请号：US16193171

申请日：2018-11-16

申请人： Micron Technology, Inc.

发明人： Ting Luo ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Xiangang Luo ,  Renato Padilla, Jr. ,  Gary F. Besinga ,  Sampath Ratnam ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

摘要： Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.

公开(公告)号：US20210027846A1

公开(公告)日：2021-01-28

申请号：US17035149

申请日：2020-09-28

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

IPC分类号： G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

摘要： Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US10719271B2

公开(公告)日：2020-07-21

申请号：US16193126

申请日：2018-11-16

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Karl D. Schuh ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam ,  Harish Reddy Singidi ,  Renato Padilla, Jr.

IPC分类号： G11C7/04 ,  G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04

摘要： Various examples are directed to systems and methods of managing a memory device. The memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

公开(公告)号：US10672452B2

公开(公告)日：2020-06-02

申请号：US16138115

申请日：2018-09-21

申请人： Micron Technology, Inc.

发明人： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC分类号： G11C7/00 ,  G11C11/406 ,  G06F13/16

摘要： Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.

公开(公告)号：US20200159447A1

公开(公告)日：2020-05-21

申请号：US16193171

申请日：2018-11-16

申请人： Micron Technology, Inc.

发明人： Ting Luo ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Xiangang Luo ,  Renato Padilla, JR. ,  Gary F. Besinga ,  Sampath Ratnam ,  Vamsi Pavan Rayaprolu

IPC分类号： G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G11C16/34

摘要： Various examples are directed to systems and methods for reading a memory component. A processing device may receive an indication that a read operation at a physical address of the memory component failed. The processing device may execute a plurality of read retry operations at the physical address. The processing device may access a first syndrome weight describing a first error correction operation performed on a result of a first read retry operation of the plurality of read retry operations and a second syndrome weight describing a second error correction operation performed on a result of a second read retry operation of the plurality of read retry operations. The processing device may select a first threshold voltage associated with the first read retry operation based at least in part on the first syndrome weight and the second syndrome weight. The processing device may also execute a first auto read calibrate operation at the physical address, the first auto read calibrate operation having a baseline at the first threshold voltage.

公开(公告)号：US10586602B2

公开(公告)日：2020-03-10

申请号：US16436567

申请日：2019-06-10

申请人： Micron Technology, Inc.

发明人： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC分类号： G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02 ,  G11C16/24 ,  G11C16/08

摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.