公开(公告)号：US11901334B2

公开(公告)日：2024-02-13

申请号：US17087867

申请日：2020-11-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

CPC classification number: H01L25/0655 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/18 ,  H01L2924/0001

Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.

公开(公告)号：US11640948B2

公开(公告)日：2023-05-02

申请号：US17198447

申请日：2021-03-11

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US11469210B2

公开(公告)日：2022-10-11

申请号：US16551072

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

公开(公告)号：US20210090985A1

公开(公告)日：2021-03-25

申请号：US17110035

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

公开(公告)号：US10446509B2

公开(公告)日：2019-10-15

申请号：US16039652

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US10128212B2

公开(公告)日：2018-11-13

申请号：US15676350

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L25/065

Abstract: A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be coupled to both the first logic die and the second logic die on a first active face of the first logic die and a second active face of the second logic die. A redistribution layer (RDL) structure may be coupled to the first logic die, the second logic die, and the bridge memory die. The bridge memory die may be interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure. A molding compound may at least partially encapsulate the first logic die, the second logic die, and the bridge memory die.

公开(公告)号：US10043769B2

公开(公告)日：2018-08-07

申请号：US14730231

申请日：2015-06-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US10026680B2

公开(公告)日：2018-07-17

申请号：US15725723

申请日：2017-10-05

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L21/304 ,  H01L21/56 ,  H01L21/58 ,  H01L21/78 ,  H01L23/498 ,  H01L21/52 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.

公开(公告)号：US20170323866A1

公开(公告)日：2017-11-09

申请号：US15660210

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

公开(公告)号：US09786514B2

公开(公告)日：2017-10-10

申请号：US15296058

申请日：2016-10-18

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2924/1511 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2224/81

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side of the RDL interposer.