公开(公告)号：US20130288466A1

公开(公告)日：2013-10-31

申请号：US13929590

申请日：2013-06-27

Applicant: Micron Technology, Inc.

Inventor： Lequn Jennifer Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

IPC: H01L21/223

CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

公开(公告)号：US20130233834A1

公开(公告)日：2013-09-12

申请号：US13868886

申请日：2013-04-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shu Qin

IPC: H01L21/67 ,  B23K10/00

CPC classification number: H01L21/67109 ,  B23K10/00 ,  H01J37/32522 ,  H01J37/32935 ,  H01J2237/2001 ,  H01L21/2636 ,  H01L21/67248

Abstract: Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature.

Abstract translation: 本文公开了快速热处理系统和相关方法。 在一个实施例中，用于加热微电子衬底的方法包括产生等离子体，将所产生的等离子体施加到微电子衬底的表面，以及利用所产生的等离子体将微电子衬底的温度提高到微电子衬底的表面。 该方法还包括继续施加所产生的等离子体，直到微电子衬底达到所需温度。

公开(公告)号：US20240363384A1

公开(公告)日：2024-10-31

申请号：US18767938

申请日：2024-07-09

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Ming Zhang

IPC: H01L21/683 ,  H01L21/762

CPC classification number: H01L21/6833 ,  H01L21/76251

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

公开(公告)号：US12040211B2

公开(公告)日：2024-07-16

申请号：US18165119

申请日：2023-02-06

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Ming Zhang

IPC: H01L21/683 ,  H01L21/762

CPC classification number: H01L21/6833 ,  H01L21/76251

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

公开(公告)号：US11574834B2

公开(公告)日：2023-02-07

申请号：US17395389

申请日：2021-08-05

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Ming Zhang

IPC: H01L21/683 ,  H01L21/762

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

公开(公告)号：US20190096732A1

公开(公告)日：2019-03-28

申请号：US16206895

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Ming Zhang

IPC: H01L21/683 ,  H01L21/762

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

公开(公告)号：US09530842B2

公开(公告)日：2016-12-27

申请号：US14597766

申请日：2015-01-15

Applicant: Micron Technology, Inc.

Inventor： Shu Qin ,  Yongjun Jeff Hu ,  Allen McTeer

IPC: H01L29/76 ,  H01L29/08 ,  H01L29/45 ,  H01L21/223 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/823418 ,  H01L27/092 ,  H01L29/456 ,  H01L29/665

Abstract: Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. Some embodiments include a method in which first boron-enhanced regions are formed within upper portions of n-type source/drain regions of an NMOS (n-type metal-oxide-semiconductor) device and second boron-enhanced regions are simultaneously formed within upper portions of p-type source/drain regions of a PMOS (p-type metal-oxide-semiconductor) device. The first and second boron-enhanced regions extend to depths of less than or equal to about 10 nanometers.

Abstract translation: 一些实施例包括具有n型扩散区的器件，并且在n型扩散区内具有硼掺杂区。 硼掺杂区从n型扩散区的上表面延伸不超过约10纳米。 一些实施例包括其中在NMOS（n型金属氧化物半导体）器件的n型源极/漏极区的上部形成第一硼增强区的方法，并且第二硼增强区同时形成在上部 PMOS（p型金属氧化物半导体）器件的p型源/漏区的部分。 第一和第二硼增强区域延伸到小于或等于约10纳米的深度。

公开(公告)号：US20160284996A1

公开(公告)日：2016-09-29

申请号：US15176609

申请日：2016-06-08

Applicant: Micron Technology, Inc.

Inventor： Martin Schubert ,  Shu Qin ,  Scott E. Sills ,  Dural Vishak Nirmal Ramaswamy ,  Allen McTeer ,  Yongjun Jeff Hu

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.

公开(公告)号：US20160218282A1

公开(公告)日：2016-07-28

申请号：US15090292

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

公开(公告)号：US20160190209A1

公开(公告)日：2016-06-30

申请号：US15063179

申请日：2016-03-07

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Swapnil Lengade ,  Everett Allen McTeer ,  Shu Qin

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.