公开(公告)号：US20210072987A1

公开(公告)日：2021-03-11

申请号：US16841222

申请日：2020-04-06

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US20250124102A1

公开(公告)日：2025-04-17

申请号：US18757909

申请日：2024-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dmitri Yudanov ,  Lawrence Celso Miranda ,  Sheyang Ning ,  Aliasger Zaidy

IPC: G06F17/16

Abstract: Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.

公开(公告)号：US20250069629A1

公开(公告)日：2025-02-27

申请号：US18786480

申请日：2024-07-27

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  James B. Johnson ,  Peter L. Brown ,  Glen E. Hush

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/22

Abstract: Processing can occur in registers of a memory sub-system. A first plurality of registers coupled to the plurality of sense amplifiers can store the first plurality of bits received from the plurality of sense amplifiers. Processing circuitry coupled to the first plurality of registers can receive the first plurality of bits from the first plurality of registers and can perform an operation on the first plurality of bits to generate result bits. A second plurality of registers coupled to the processing circuitry and the plurality of registers can store the result bits received from the processing circuitry and can provide the result bits to a plurality of data input/output (I/O) lines prior to storing a second plurality of bits.

公开(公告)号：US20250028676A1

公开(公告)日：2025-01-23

申请号：US18906534

申请日：2024-10-04

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06N3/063 ,  G06T1/20 ,  G06T1/60

Abstract: The present disclosure is directed to a distributed graphics processor unit (GPU) architecture that includes an array of processing nodes. Each processing node may include a GPU node that is coupled to its own fast memory unit and its own storage unit. The fast memory unit and storage unit may be integrated into a single unit or may be separately coupled to the GPU node. The processing node may have its fast memory unit coupled to both the GPU node and the storage node. The various architectures provide a GPU-based system that may be treated as a storage unit, such as solid state drive (SSD) that performs onboard processing to perform memory-oriented operations. In this respect, the system may be viewed as a “smart drive” for big-data near-storage processing.

公开(公告)号：US12135985B2

公开(公告)日：2024-11-05

申请号：US17898642

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/48 ,  G06F9/38 ,  G06F11/30 ,  G06F11/34 ,  G11C11/409

Abstract: Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.

公开(公告)号：US20240345957A1

公开(公告)日：2024-10-17

申请号：US18751020

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/0837 ,  G06F9/38 ,  G06F11/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06N3/02

CPC classification number: G06F12/0837 ,  G06F9/3877 ,  G06F11/1448 ,  G06F12/1009 ,  G06F12/1027 ,  G06N3/02

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US12111789B2

公开(公告)日：2024-10-08

申请号：US16855879

申请日：2020-04-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F15/80 ,  G06N3/063 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F15/8092 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/5083 ,  G06N3/063 ,  G06T1/20 ,  G06T1/60

Abstract: The present disclosure is directed to a distributed graphics processor unit (GPU) architecture that includes an array of processing nodes. Each processing node may include a GPU node that is coupled to its own fast memory unit and its own storage unit. The fast memory unit and storage unit may be integrated into a single unit or may be separately coupled to the GPU node. The processing node may have its fast memory unit coupled to both the GPU node and the storage node. The various architectures provide a GPU-based system that may be treated as a storage unit, such as solid state drive (SSD) that performs onboard processing to perform memory-oriented operations. In this respect, the system may be viewed as a “smart drive” for big-data near-storage processing.

公开(公告)号：US12056599B2

公开(公告)日：2024-08-06

申请号：US18061005

申请日：2022-12-02

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC: G06N3/00 ,  G06F3/06 ,  G06N3/04 ,  G06N3/063 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

CPC classification number: G06N3/063 ,  G06F3/0604 ,  G06F3/0661 ,  G06F3/0673 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a bit line and a word line of a number of word lines. A number of signals corresponding to bits of a second number may be driven on the number of word lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US11954042B2

公开(公告)日：2024-04-09

申请号：US17943739

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

CPC classification number: G06F12/10 ,  H04L67/1097 ,  G06F2212/154 ,  G06F2212/657 ,  H04W84/042

Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US20240078187A1

公开(公告)日：2024-03-07

申请号：US18500978

申请日：2023-11-02

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/0893

CPC classification number: G06F12/0893 ,  G06F2212/608

Abstract: The disclosed embodiments relate to per-process configuration caches in storage devices. A method is disclosed comprising initiating a new process, the new process associated with a process context; configuring a region in a memory device, the region associated with the process context, wherein the configuring comprises setting one or more cache parameters that modify operation of the memory device; and mapping the process context to the region of the memory device