公开(公告)号：US20220068959A1

公开(公告)日：2022-03-03

申请号：US17068430

申请日：2020-10-12

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220068944A1

公开(公告)日：2022-03-03

申请号：US17006634

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11244954B2

公开(公告)日：2022-02-08

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20220020768A1

公开(公告)日：2022-01-20

申请号：US17491752

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

公开(公告)号：US20220020763A1

公开(公告)日：2022-01-20

申请号：US16928345

申请日：2020-07-14

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises an upper stack above a lower stack. The lower stack comprises vertically-alternating lower conductive tiers and lower insulative tiers. The upper stack comprises vertically-alternating upper conductive tiers and upper insulative tiers. An intervening tier is vertically between the upper and lower stacks. The intervening tier is at least predominantly polysilicon and of different composition from compositions of the upper conductive tier and the upper insulative tier immediately-above the intervening tier and of different composition from compositions of the lower conductive tier and the lower insulative tier immediately-below the intervening tier. Channel-material strings of memory cells extend through the upper stack, the intervening tier, and the lower stack. Other structures and methods are disclosed.

公开(公告)号：US20210358951A1

公开(公告)日：2021-11-18

申请号：US17391453

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Justin B. Dorhout ,  Nirup Bandaru ,  Damir Fazil ,  Nancy M. Lomeli ,  Jivaan Kishore Jhothiraman ,  Purnima Narayanan

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210358930A1

公开(公告)日：2021-11-18

申请号：US15931299

申请日：2020-05-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.

公开(公告)号：US11139386B2

公开(公告)日：2021-10-05

申请号：US16807388

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H01L29/66 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier. The conducting material less-than-fills the void-space in the lowest first tier. The conducting material is etched from the lowest first tier. After the etching of the conducting material, conductive material is deposited into the void-space of the lowest first tier and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Additional embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210287990A1

公开(公告)日：2021-09-16

申请号：US16820046

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20210287989A1

公开(公告)日：2021-09-16

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.