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    Substrate processing apparatus
    41.
    发明授权
    Substrate processing apparatus 有权
    基板加工装置

    公开(公告)号：US07854821B2

    公开(公告)日：2010-12-21

    申请号：US11445385

    申请日：2006-06-02

    申请人： Hiroshi Nakamura ,  Seiichi Kaise

    发明人： Hiroshi Nakamura ,  Seiichi Kaise

    IPC分类号： H01L21/00

    CPC分类号： H01L21/67109 ,  H01J37/32082 ,  H01J2237/2001 ,  H01L21/67253 ,  H01L21/67276 ,  H01L21/67742 ,  Y10T279/23

    摘要： A substrate processing apparatus includes a heat transfer gas supply mechanism to supply a heat transfer gas through a supply passage into a portion between a worktable and a substrate to improve thermal conductivity between therebetween. Under the control of a control section, the pressure inside the supply passage is measured to obtain a pressure measurement value while the substrate is placed on the worktable. Then, a preparatory flow rate of the heat transfer gas to be supplied through the supply passage into the portion between the worktable and substrate is determined, in accordance with the pressure difference between the pressure measurement value and a pressure reference value, prior to a main process to be performed on the substrate. Then, the heat transfer gas is supplied through the supply passage into the portion between the worktable and substrate at the preparatory flow rate, prior to the main process.

    摘要翻译： 基板处理装置包括：传热气体供给机构，用于将传热气体通过供给通道供应到工作台和基板之间的部分，以提高它们之间的导热性。 在控制部分的控制下，测量供给通道内的压力，以便在将基板放置在工作台上时获得压力测量值。 然后，根据压力测量值和压力基准值之间的压力差，在主体之间确定通过供给通道供给到工作台和基板之间的部分的传热气体的预备流量 在基板上进行的处理。 然后，在主工序之前，传热气体以预备流量通过供给通道供给到工作台和基板之间的部分。

    SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE
    42.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE 有权
    仅使用单通道晶体管将电压施加到选定字线的半导体存储器件

    公开(公告)号：US20100309724A1

    公开(公告)日：2010-12-09

    申请号：US12856962

    申请日：2010-08-16

    申请人： Hiroshi Nakamura ,  Kenichi Imamiya

    发明人： Hiroshi Nakamura ,  Kenichi Imamiya

    IPC分类号： G11C16/04

    CPC分类号： G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459 ,  H01L27/115

    摘要： A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

    摘要翻译： 半导体存储器件具有存储单元阵列，第一导电类型的第一晶体管，第二导电类型的第二晶体管和第一导电类型的第三晶体管。 第一晶体管的源极或漏极连接到每条字线。 第二晶体管的漏极连接到第一晶体管的栅极。 第三晶体管的源极连接到第一晶体管的栅极。 第二晶体管和第三晶体管的栅极不连接，第二晶体管的源极不连接到第三晶体管的漏极，并且第二晶体管的栅极和第三晶体管的漏极具有不同的电压电平 彼此相反的逻辑水平。

    Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
    44.
    发明授权
    Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
    半导体存储器件能够实现具有高操作可靠性和高产量的芯片

    公开(公告)号：US07787277B2

    公开(公告)日：2010-08-31

    申请号：US12052882

    申请日：2008-03-21

    申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

    发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

    IPC分类号： G11C11/34

    CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

    摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

    Developing blade
    45.
    发明授权
    Developing blade 失效
    开发刀片

    公开(公告)号：US07783237B2

    公开(公告)日：2010-08-24

    申请号：US12281150

    申请日：2007-05-18

    申请人： Shinji Souma ,  Hiroshi Nakamura

    发明人： Shinji Souma ,  Hiroshi Nakamura

    IPC分类号： G03G15/08

    CPC分类号： G03G15/0812 ,  C08G77/04 ,  C08K3/04 ,  C08K3/041 ,  C08K3/045 ,  C08L23/04 ,  C08L83/04 ,  G03G2215/0634 ,  Y02P20/123 ,  C08L2666/06 ,  C08L2666/04

    摘要： The blade member of the invention is composed mainly of silicone rubber and contains as an additive component at least one selected from the group consisting of ultra-high molecular-weight-polyethylene, carbon nanotube, and fullerene. It is thus possible to decrease the coefficient of friction of silicone rubber in a practical range and without detrimental to its flexibility or other physical properties to let the developing blade slip off more, thereby diminishing the amount of abrasion of the rubber and improving on the robustness of the developing blade without detrimental to image quality. Decreasing the coefficient of friction to let the developing blade slip off more has additional advantages: a decrease in the force of contact of the developing blade with a developing roll, which contributes more to energy savings resulting from the size reductions of a driving motor, and making the developer equipment compact.

    摘要翻译： 本发明的叶片构件主要由硅橡胶构成，作为添加成分，含有选自超高分子量聚乙烯，碳纳米管和富勒烯中的至少一种。 因此，可以在实用的范围内降低硅橡胶的摩擦系数，并且不会对其柔性或其他物理性质产生不利影响，从而使显影刮板脱落更多，从而减少橡胶的磨损量并提高其坚固性 的显影刀片，而不损害图像质量。 降低摩擦系数以使显影刮板滑落更多具有另外的优点：显影刮板与显影辊的接触力降低，这对于由于驱动电机的尺寸减小而导致的能量节省更多;以及 使开发设备紧凑。

    NAND-type EEPROM with increased reading speed
    46.
    发明授权
    NAND-type EEPROM with increased reading speed 有权
    NAND型EEPROM具有增加的读取速度

    公开(公告)号：US07768057B2

    公开(公告)日：2010-08-03

    申请号：US11969740

    申请日：2008-01-04

    申请人： Hiroshi Nakamura ,  Kenichi Imamiya

    发明人： Hiroshi Nakamura ,  Kenichi Imamiya

    IPC分类号： H01L29/94 ,  H01L23/62

    CPC分类号： H01L27/11526 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

    摘要翻译： 在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压Vread与电压Vsg1，Vsg2 在所选择的块中选择晶体管的选择栅极，从而使得可以实现高速读取，而不会导致插入在选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。 如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。 选择晶体管的栅极。

    Non-Volatile Semiconductor Memory
    49.
    发明申请
    Non-Volatile Semiconductor Memory 有权
    非易失性半导体存储器

    公开(公告)号：US20100061149A1

    公开(公告)日：2010-03-11

    申请号：US12621134

    申请日：2009-11-18

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

    摘要翻译： 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

    HEAT EXCHANGER
    50.
    发明申请
    HEAT EXCHANGER 审中-公开
    热交换器

    公开(公告)号：US20100051248A1

    公开(公告)日：2010-03-04

    申请号：US12515740

    申请日：2007-11-20

    申请人： Takanari Inatomi ,  Hiroshi Nakamura ,  Kazuyoshi Aoki ,  Shigeki Maruyama

    发明人： Takanari Inatomi ,  Hiroshi Nakamura ,  Kazuyoshi Aoki ,  Shigeki Maruyama

    IPC分类号： F28F3/04 ,  F28F21/08 ,  F28F3/08

    CPC分类号： F28D9/0037 ,  F28F3/04 ,  F28F2250/102

    摘要： A stacked plate type heat exchanger having compactness and providing a heat exchanging rate per unit volume of 10 MWt/m3 or more is used under conditions of high temperature and high pressure of 4 to 7 MPa of pressure difference between a primary fluid and a secondary fluid, and 500° C. to 900° C. of maximum operating temperature. A thickness of metal plate is set at 0.3 times or more of an equivalent diameter of a flow path, and a pitch between flow paths along a width direction of the metal plate is set at 0.5 times or more of the equivalent diameter of the flow path.

    摘要翻译： 在初级流体和次级流体之间的压力差为4〜7MPa的高温高压的条件下，使用具有紧凑性且每单位体积的10Mt / m 3以上的热交换率的层叠型热交换器 ，最高工作温度为500〜900℃。 将金属板的厚度设定为流路的等效直径的0.3倍以上，将沿着金属板的宽度方向的流路间的间距设定为流路的等效直径的0.5倍以上 。