公开(公告)号：US06762448B1

公开(公告)日：2004-07-13

申请号：US10405343

申请日：2003-04-03

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L2708

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

Abstract translation: 半导体器件包括一组翅片结构。 翅片结构的组包括导电材料，并且通过在氧化物层的开口中生长导电材料而形成。 半导体器件还包括形成在鳍片结构组的一端处的源极区域，形成在鳍片结构组的相对端处的漏极区域和至少一个栅极。

公开(公告)号：US06566212B1

公开(公告)日：2003-05-20

申请号：US09761953

申请日：2001-01-17

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a solid-phase impurity source. The solid-phase impurity source can be a doped silicon dioxide layer approximately 300 nm thick. The structure is thermally annealed to drive dopants from the solid-phase impurity source into the source and drain regions. The dopants from the impurity source provide ultra-shallow source and drain extensions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用固相杂质源。 固相杂质源可以是约300nm厚的掺杂二氧化硅层。 该结构被热退火以将来自固相杂质源的掺杂剂驱动到源区和漏区。 来自杂质源的掺杂剂提供超浅源极和漏极延伸。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06531753B1

公开(公告)日：2003-03-11

申请号：US10174046

申请日：2002-06-18

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L2912

CPC classification number: H01L21/76251

Abstract: A silicon-on-insulator substrate is disclosed which comprises: a silicon substrate layer; a first insulation layer over the silicon substrate layer; a conductive layer over the first insulation layer comprising at least one metal or metal silicide over the first insulation layer; a second insulation layer over the conductive layer; a silicon device layer comprising silicon over the second insulation layer; at least first conductive plug through the silicon substrate and the first insulation layer contacting the conductive layer; and at least one second conductive plug through the silicon device layer and the second insulation layer contacting the conductive layer. Also disclosed are methods for forming silicon-on-insulator substrates having improved stable ground characteristics.

Abstract translation: 公开了一种绝缘体上硅衬底，其包括：硅衬底层; 硅衬底层上的第一绝缘层; 所述第一绝缘层上的导电层包括在所述第一绝缘层上的至少一种金属或金属硅化物; 导电层上的第二绝缘层; 在第二绝缘层上包含硅的硅器件层; 穿过硅衬底的至少第一导电插塞和与导电层接触的第一绝缘层; 以及穿过所述硅器件层和所述第二绝缘层接触所述导电层的至少一个第二导电插塞。 还公开了用于形成具有改进的稳定接地特性的绝缘体上硅衬底的方法。

公开(公告)号：US06486038B1

公开(公告)日：2002-11-26

申请号：US09804360

申请日：2001-03-12

Applicant: Witold P. Maszara ,  Ming-Ren Lin ,  Qi Xiang

Inventor： Witold P. Maszara ,  Ming-Ren Lin ,  Qi Xiang

IPC: H01L2176

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; (b) etching the silicon active layer to form an isolation trench wherein an unetched silicon layer at bottom of the isolation trench remains; (c) oxidizing the layer of silicon at the bottom of the isolation trench to a degree sufficient to oxidize through the layer of silicon at the bottom to the dielectric isolation layer; and (d) filling the isolation trench with a trench isolation material to form a shallow trench isolation structure.

Abstract translation: 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（a）提供具有硅有源层，介电隔离层和硅衬底的绝缘体上硅半导体晶片，其中 在介电隔离层上形成硅有源层，并在硅衬底上形成电介质隔离层; （b）蚀刻硅有源层以形成隔离沟槽，其中保留隔离沟槽底部的未蚀刻硅层; （c）将隔离沟槽的底部的硅层氧化至足以通过底部的硅层氧化成电介质隔离层的程度; 和（d）用沟槽隔离材料填充隔离沟槽以形成浅沟槽隔离结构。

公开(公告)号：US06483147B1

公开(公告)日：2002-11-19

申请号：US09427135

申请日：1999-10-25

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L2701

CPC classification number: H01L21/743 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, the present invention relates to a method of facilitating heat removal from a device layer of a silicon-on-insulator substrate comprising bulk silicon, an insulation layer over the bulk silicon, and a silicon device layer over the insulation layer involving forming at least one conductive plug comprising a conductive material within the bulk silicon and the insulation layer so as to contact the silicon device layer. In another embodiment, the present invention relates to a silicon-on-insulator structure, made of a silicon substrate layer; an insulation layer over the silicon substrate layer; a silicon device layer comprising silicon over the insulation layer; a conductive plug through the silicon substrate layer and the insulation layer contacting the silicon device layer; and a heat generating structure on the silicon device layer at least partially overlapping the conductive plug.

Abstract translation: 在一个实施例中，本发明涉及一种促进从绝缘体上硅衬底的器件层的散热的方法，其包括体硅，体硅上的绝缘层和绝缘层上的硅器件层，包括形成 至少一个导电插塞，其包括本体硅内的导电材料和绝缘层，以便与硅器件层接触。 在另一个实施例中，本发明涉及由硅衬底层制成的绝缘体上硅结构; 硅衬底层上的绝缘层; 在所述绝缘层上包含硅的硅器件层; 穿过硅衬底层的导电插塞和与硅器件层接触的绝缘层; 以及在硅器件层上的至少部分地与导电插塞重叠的发热结构。

公开(公告)号：US06458639B1

公开(公告)日：2002-10-01

申请号：US09773828

申请日：2001-01-31

Applicant: Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

Inventor： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC: H01L2974

CPC classification number: H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract translation: 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06274420B1

公开(公告)日：2001-08-14

申请号：US09510786

申请日：2000-02-23

Applicant: Qi Xiang ,  Wei Long ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC: H01L218238

CPC classification number: H01L29/665 ,  H01L21/76224

Abstract: STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

Abstract translation: 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。

公开(公告)号：US6159782A

公开(公告)日：2000-12-12

申请号：US369217

申请日：1999-08-05

Applicant: Qi Xiang ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823857 ,  H01L29/66545

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the layer of dielectric has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 600.degree. Celsius, using a solid phase crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon. Thus, relatively low temperatures are used in the present invention to preserve the integrity of the gate dielectric having the high dielectric constant.

Abstract translation: 一种用于制造具有双栅极和具有高介电常数的栅极电介质的短沟道场效应晶体管的方法。 场效应晶体管最初被制造成具有牺牲栅极电介质和虚拟栅电极。 使用具有牺牲栅极电介质和虚拟栅电极的场效应晶体管，使用相对较高的温度进行任何制造工艺，例如场效应晶体管的源极和漏极的激活退火或腐蚀退火。 从场效应晶体管蚀刻伪栅电极和牺牲栅电介质以形成栅极开口。 在栅极的侧壁和底壁上沉积具有高介电常数的电介质层，并沉积诸如非晶硅之类的非晶态栅电极材料，以在沉积介电层之后填充栅极开口。 通过用N型掺杂剂掺杂非晶栅电极材料来形成用于N沟道场效应晶体管和P沟道场效应晶体管的双栅极，并且通过掺杂非晶栅电极 具有用于P沟道场效应晶体管的P型掺杂剂的材料。 然后，使用固相结晶工艺，在诸如600℃的较低温度下将栅极开口中的非晶栅电极材料退火，将非晶态的非晶硅等非晶态栅电极材料转换为多晶栅电极材料， 作为多晶硅。 因此，在本发明中使用相对较低的温度来保持具有高介电常数的栅极电介质的完整性。

公开(公告)号：US6083798A

公开(公告)日：2000-07-04

申请号：US84322

申请日：1998-05-26

Applicant: Ming-Ren Lin

Inventor： Ming-Ren Lin

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66492 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7833 ,  H01L21/2257

Abstract: A semiconductor device and a method of making the device with a raised source/drain has a semiconductive material that is non-selectively deposited in a layer over the device area. The semiconductive material is then etched to form spacers that will form the raised soure/drain areas following doping of the spacers. The gate of the semiconductor device is protected during the etching by an etch stop layer that is grown or deposited over the structure to be protected, e.g., the gate, prior to the deposition of the semiconductive material layer. Lightly doped drain ion implantation is performed prior to the formation of the spacers, and source-drain ion implantation is performed preferably after the formation of the spacers, to create the shallow junctions.

Abstract translation: 半导体器件和使具有升高的源极/漏极的器件的方法具有非选择性地沉积在器件区域上的层中的半导体材料。 然后蚀刻半导体材料以形成在掺杂间隔物之后将形成升高的固体/漏极区的间隔物。 半导体器件的栅极在蚀刻期间被保护，该蚀刻停止层在沉积半导体材料层之前生长或沉积在要保护的结构（例如栅极）上。 在形成间隔物之前进行轻掺杂的漏极离子注入，优选在形成间隔物之后进行源极 - 漏极离子注入，以产生浅结。

公开(公告)号：US5904528A

公开(公告)日：1999-05-18

申请号：US785213

申请日：1997-01-17

Applicant: Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

Inventor： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

IPC: H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L21/823814 ,  H01L29/7835

Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.