公开(公告)号：US5614765A

公开(公告)日：1997-03-25

申请号：US478319

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1036 ,  H01L2924/0002

Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.

Abstract translation: 用于集成电路和用于半导体器件的衬底载体的绝缘分隔的导线和连接通孔的互连级别，使用双镶嵌仅具有一个掩模图案以形成导电线和通孔。 导电线的掩模图案包含​​在绝缘材料中要形成通孔开口的横向扩大区域。 在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于 绝缘材料到其附魔。 保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。 侧壁用作通过开口蚀刻的自对准掩模。 保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。 在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。 在后者中，导电线路开口和通孔用相同的导电材料填充。

公开(公告)号：US08502283B2

公开(公告)日：2013-08-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US20090047770A1

公开(公告)日：2009-02-19

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07329582B1

公开(公告)日：2008-02-12

申请号：US11154785

申请日：2005-06-15

Applicant: James Pan ,  Jonathan Byron Smith ,  Ming-Ren Lin

Inventor： James Pan ,  Jonathan Byron Smith ,  Ming-Ren Lin

IPC: H01L21/335

CPC classification number: H01L29/41775 ,  H01L21/2652 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/288 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for fabricating a semiconductor device having an impurity doped region in a silicon substrate. The method comprises forming a metal silicide layer electrically contacting the impurity doped region and depositing a conductive layer overlying and electrically contacting the metal silicide layer. A dielectric layer is deposited overlying the conductive layer and an opening is etched through the dielectric layer to expose a portion of the conductive layer. A conductive material is selectively deposited to fill the opening and to electrically contact the impurity doped region.

Abstract translation: 提供了制造在硅衬底中具有杂质掺杂区的半导体器件的方法。 该方法包括形成与杂质掺杂区电接触的金属硅化物层，并沉积覆盖并电接触金属硅化物层的导电层。 沉积覆盖导电层的电介质层，并且通过电介质层蚀刻开口以暴露导电层的一部分。 选择性地沉积导电材料以填充开口并与杂质掺杂区域电接触。

公开(公告)号：US07306997B2

公开(公告)日：2007-12-11

申请号：US10986399

申请日：2004-11-10

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L21/336

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US06800910B2

公开(公告)日：2004-10-05

申请号：US10335474

申请日：2002-12-31

Applicant: Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

Inventor： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

IPC: H01L27105

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

Abstract translation: FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。 然后在硅锗FinFET体上形成硅的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：US06764898B1

公开(公告)日：2004-07-20

申请号：US10147690

申请日：2002-05-16

Applicant: William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

Inventor： William G. En ,  Joong S. Jeon ,  Minh Van Ngo ,  Ming-Ren Lin

IPC: H01L218242

CPC classification number: H01L21/28273 ,  H01L21/2807 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31691 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: The present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching. As a result of the implantation, the etch rate of the selected portion is increased relative to an etch rate without the implanting.

Abstract translation: 本发明涉及制造半导体器件的方法，包括提供半导体晶片的步骤; 在半导体晶片上沉积包含高K电介质材料层的至少一层; 并且随后通过将离子注入所选择的部分中去除包含高K电介质材料的至少一层的选定部分，以及通过蚀刻去除所选择的部分。 作为植入的结果，所选择的部分的蚀刻速率相对于没有植入的蚀刻速率而增加。

公开(公告)号：US06291278B1

公开(公告)日：2001-09-18

申请号：US09303694

申请日：1999-05-03

Applicant: Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Matthew S. Buynoski ,  Ming-Ren Lin

IPC: H01L21336

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/823871 ,  H01L29/66545

Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

Abstract translation: 制造具有浅源极和漏极延伸的晶体管的方法利用自对准接触。 漏极延伸部分通过接触区域和栅极结构之间的开口提供。 可以使用高K栅介电材料。 可以根据所公开的方法创建P-MOS和N-MOS晶体管。

公开(公告)号：US06169039A

公开(公告)日：2001-01-02

申请号：US09187169

申请日：1998-11-06

Applicant: Ming-Ren Lin ,  Shekhar Pramanick ,  David Bang

Inventor： Ming-Ren Lin ,  Shekhar Pramanick ,  David Bang

IPC: H01L2131

CPC classification number: H01L21/02118 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02351 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3124 ,  Y02P80/30

Abstract: An integrated circuit and a method of forming an integrated circuit is described. The integrated circuit includes a silicon substrate, a dielectric stack formed on the silicon substrate, and conductive metal lines overlying the silicon substrate. A first layer of low-k dielectric material overlies the at least one conductive metal line, and a second layer of low-k dielectric material overlies the first layer of low-k dielectric material. The first layer of low-k dielectric material is electron beam (E-beam) cured and the second layer of low-k dielectric material is thermally cured.

Abstract translation: 描述集成电路和形成集成电路的方法。 集成电路包括硅衬底，形成在硅衬底上的电介质叠层和覆盖硅衬底的导电金属线。 低k电介质材料的第一层覆盖在至少一个导电金属线上，第二低k电介质材料层覆盖在第一低电介质材料层上。 第一层低k电介质材料是电子束（电子束）固化，第二层低k介电材料被热固化。

公开(公告)号：US6140186A

公开(公告)日：2000-10-31

申请号：US196439

申请日：1998-11-20

Applicant: Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

Inventor： Ming-Ren Lin ,  Peng Fang ,  Donald L. Wollesen

IPC: H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L21/823814 ,  H01L29/7835

Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

Abstract translation: 晶体管的不对称掺杂的源极/漏极区域使用保护绝缘层形成，以防止栅电极的一部分接收到过多的杂质注入剂量，并穿过下面的栅极绝缘层进入半导体衬底。 在重植入期间采用侧壁间隔物。