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公开(公告)号：US20180019713A1
公开(公告)日：2018-01-18
申请号：US15717161
申请日：2017-09-27
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuo WATANABE , Satoshi TANAKA , Kazuhito NAKAI , Takayuki TSUTSUI
CPC classification number: H03F1/3205 , H03F1/02 , H03F1/0261 , H03F1/302 , H03F1/32 , H03F3/19 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/18 , H03F2200/21 , H03F2200/451 , H03F2201/3215 , H03F2203/21106 , H04B1/0475 , H04B2001/045
Abstract: A power amplification module includes: a first transistor that amplifies a first radio frequency signal and outputs a second radio frequency signal; a second transistor that amplifies the second radio frequency signal and outputs a third radio frequency signal; and first and second bias circuits that supply first and second bias currents to bases of the first and second transistors. The first bias circuit includes a third transistor that outputs the first bias current from its emitter or source, a capacitor that is input with the first radio frequency signal and connected to the base of the first transistor, a first resistor connected between the emitter or source of the third transistor and the base of the first transistor, a second resistor connected between the capacitor and the emitter or source of the third transistor, and a third resistor connected between the capacitor and the base of the first transistor.
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公开(公告)号：US20170155367A1
公开(公告)日：2017-06-01
申请号：US15274313
申请日：2016-09-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Kazuo WATANABE , Satoshi TANAKA , Kazuhito NAKAI , Takayuki TSUTSUI
CPC classification number: H03F1/3205 , H03F1/02 , H03F1/0261 , H03F1/302 , H03F1/32 , H03F3/19 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/18 , H03F2200/21 , H03F2200/451 , H03F2201/3215 , H03F2203/21106 , H04B1/0475 , H04B2001/045
Abstract: A power amplification module includes: a first transistor that amplifies a first radio frequency signal and outputs a second radio frequency signal; a second transistor that amplifies the second radio frequency signal and outputs a third radio frequency signal; and first and second bias circuits that supply first and second bias currents to bases of the first and second transistors. The first bias circuit includes a third transistor that outputs the first bias current from its emitter or source, a capacitor that is input with the first radio frequency signal and connected to the base of the first transistor, a first resistor connected between the emitter or source of the third transistor and the base of the first transistor, a second resistor connected between the capacitor and the emitter or source of the third transistor, and a third resistor connected between the capacitor and the base of the first transistor.
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公开(公告)号：US20150333702A1
公开(公告)日：2015-11-19
申请号：US14807913
申请日：2015-07-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takayuki TSUTSUI , Satoshi TANAKA , Kenichi SHIMAMOTO
CPC classification number: H03F1/0205 , H03F1/30 , H03F1/302 , H03F1/32 , H03F1/56 , H03F3/189 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/108 , H03F2200/129 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/447 , H03F2200/451 , H03F2200/555
Abstract: An radio frequency amplifying circuit includes an amplifying transistor configured to amplify a radio frequency signal input to a base of the amplifying transistor via a matching network to output the amplified radio frequency signal, a first bias transistor connected to the amplifying transistor based on a current-mirror connection to supply a bias to the amplifying transistor, and a second bias transistor connected to the base of the amplifying transistor based on an emitter-follower connection to supply a bias to the amplifying transistor.
Abstract translation: 射频放大电路包括：放大晶体管，被配置为经由匹配网络放大输入到放大晶体管的基极的射频信号，以输出放大的射频信号;第一偏置晶体管，基于电流 - 反射镜连接以向放大晶体管提供偏置;以及第二偏置晶体管，其基于发射极跟随器连接到放大晶体管的基极，以向放大晶体管提供偏置。
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公开(公告)号：US20240096792A1
公开(公告)日：2024-03-21
申请号：US18522110
申请日：2023-11-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi GOTO , Masao KONDO , Shigeki KOYA , Takayuki TSUTSUI
IPC: H01L23/528 , H01L23/00 , H01L23/64 , H01L25/065
CPC classification number: H01L23/528 , H01L23/64 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L24/16 , H01L2224/16225 , H01L2224/32227 , H01L2224/32238 , H01L2224/48229 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2924/19011
Abstract: A semiconductor module comprises a first member including a semiconductor substrate made of a compound semiconductor and a first electronic circuit on the semiconductor substrate is mounted on a mounting surface of a module substrate, and a second member including a semiconductor layer formed of a single semiconductor thinner than the semiconductor substrate of the first member and a second electronic circuit on the semiconductor layer is bonded to an upper surface of the first member. First and second pads are respectively connected to the first electronic circuit on the first member and the second electronic circuit on the second member. A first wire connects the first pad and a substrate side pad. A second wire connects the second pad and a substrate side pad. An inter-member connection wire made of a conductor film on the first and second members connects the first and second electronic circuits.
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公开(公告)号：US20220256477A1
公开(公告)日：2022-08-11
申请号：US17652136
申请日：2022-02-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Kiichiro TAKENAKA , Takayuki TSUTSUI , Taizo YAMAWAKI , Shun IMAI
Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
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Patent Agency Ranking
公开(公告)号：US20220157808A1
公开(公告)日：2022-05-19
申请号：US17504269
申请日：2021-10-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shinnosuke TAKAHASHI , Masayuki AOIKE , Takayuki TSUTSUI , Shigeki KOYA
IPC: H01L27/06 , H01L25/18 , H01L25/065 , H01L25/00 , H01L27/02
Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.
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公开(公告)号：US20210320194A1
公开(公告)日：2021-10-14
申请号：US17355048
申请日：2021-06-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Isao OBU , Yasunari UMEMOTO , Takayuki TSUTSUI , Satoshi TANAKA
IPC: H01L29/73 , H01L29/205 , H01L29/08 , H01L29/417 , H01L29/737 , H01L21/8252 , H01L21/285 , H01L21/306 , H01L21/308 , H01L29/66 , H01L27/082
Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
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公开(公告)号：US20210044263A1
公开(公告)日：2021-02-11
申请号：US17083037
申请日：2020-10-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Takayuki TSUTSUI , Satoshi TANAKA , Yasuhisa YAMAMOTO
Abstract: A power amplifier circuit amplifies a radio-frequency signal in a transmit frequency band. The power amplifier circuit includes an amplifier, a bias circuit, and an impedance circuit. The amplifier amplifies power of a radio-frequency signal and outputs an amplified signal. The impedance circuit is connected between a signal input terminal of the amplifier and a bias-current output terminal of the bias circuit and has frequency characteristics in which attenuation is obtained in the transmit frequency band. The impedance circuit includes first and second impedance circuits. The first impedance circuit is connected to the signal input terminal. The second impedance circuit is connected between the first impedance circuit and the bias-current output terminal.
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公开(公告)号：US20200374811A1
公开(公告)日：2020-11-26
申请号：US16989993
申请日：2020-08-11
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Satoshi TANAKA , Kiichiro TAKENAKA , Takayuki TSUTSUI , Taizo YAMAWAKI , Shun IMAI
Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
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公开(公告)号：US20200258882A1
公开(公告)日：2020-08-13
申请号：US16826074
申请日：2020-03-20
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shigeki KOYA , Takayuki TSUTSUI , Kazuhito NAKAI , Yusuke TANAKA
IPC: H01L27/06 , H01L23/522 , H01L23/528 , H01L29/66
Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
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