公开(公告)号：US08076718B2

公开(公告)日：2011-12-13

申请号：US11666461

申请日：2005-09-28

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Kyosuke Miyagi ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

摘要： The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

摘要翻译： 本发明的目的是提供一种绝缘栅型半导体器件及其制造方法，其中实现了高的击穿电压和紧凑性。 半导体器件具有形成在单元区域中的栅极沟槽和P浮动区域，并且具有形成在端子区域中的端子沟槽和P浮动区域。 此外，三个端子沟槽的端子沟槽具有与栅极沟槽类似的结构，而另一个端子沟槽具有填充绝缘物质如氧化硅的结构。 此外，P浮动区域51是通过从栅极沟槽的底表面注入杂质形成的区域，并且P浮动区域是通过从端子沟槽的底表面注入杂质而形成的区域。

公开(公告)号：US07667269B2

公开(公告)日：2010-02-23

申请号：US11398551

申请日：2006-04-06

申请人： Yukio Tsuzuki ,  Norihito Tokura ,  Yoshihiko Ozeki ,  Kensaku Yamamoto

发明人： Yukio Tsuzuki ,  Norihito Tokura ,  Yoshihiko Ozeki ,  Kensaku Yamamoto

IPC分类号： H01L23/62

CPC分类号： H01L29/7397 ,  H01L29/1095 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; a third semiconductor layer on the second semiconductor layer; a fourth semiconductor layer in a part of the third semiconductor layer; a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching the second semiconductor layer; a gate insulation film on an inner wall of the trench; a gate electrode on the gate insulation film in the trench; a first electrode; and a second electrode. The trench includes a bottom with a curved surface having a curvature radius equal to or smaller than 0.5 μm.

摘要翻译： 一种半导体器件包括：第一半导体层; 在所述第一半导体层上的第二半导体层; 第二半导体层上的第三半导体层; 在所述第三半导体层的一部分中的第四半导体层; 穿过第四半导体层和第三半导体层并到达第二半导体层的沟槽; 沟槽内壁上的栅极绝缘膜; 在沟槽中的栅极绝缘膜上的栅电极; 第一电极; 和第二电极。 沟槽包括具有曲率半径等于或小于0.5μm的曲面的底部。

公开(公告)号：US07498634B2

公开(公告)日：2009-03-03

申请号：US11649367

申请日：2007-01-04

申请人： Yukio Tsuzuki ,  Norihito Tokura

发明人： Yukio Tsuzuki ,  Norihito Tokura

IPC分类号： H01L29/76

CPC分类号： H01L27/0664 ,  H01L29/0834 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.

摘要翻译： 一种半导体器件包括：具有第一面和第二面的衬底; IGBT; 和二极管。 衬底包括第一层，第一层上的第二层，第二层上的第一侧N区，第一层的第二侧上的第二侧N和P区，用于栅极的第一沟槽中的第一电极 电极，第一侧N区域上的第二电极和用于发射电极和阳极电极的第二沟槽中，以及在第二侧的第三电极N和用于集电极和阴极的P区域。 第一沟槽穿过第一侧N区和第二层，并到达第一层。 第二沟槽穿过第一侧N区域并到达第二层。

公开(公告)号：US20090001411A1

公开(公告)日：2009-01-01

申请号：US12155949

申请日：2008-06-12

申请人： Norihito Tokura ,  Hiroki Sone ,  Shinji Amano ,  Hisato Kato

发明人： Norihito Tokura ,  Hiroki Sone ,  Shinji Amano ,  Hisato Kato

IPC分类号： H01L29/739

CPC分类号： H01L27/0664 ,  H01L29/407 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.

摘要翻译： 半导体器件包括形成在同一半导体衬底中的间隔沟道IGBT和反分解二极管。 IGBT包括基极层和绝缘栅极沟槽，基极层被分成连接到发射极的体区和与发射极断开的浮动区域。 IGBT形成在IGBT区域的单元区域中，二极管形成在二极管区域中。 IGBT区域的边界区域位于单元区域和二极管区域之间。 边界区域中的相邻栅极沟槽之间的间隔小于相邻栅极沟槽之间的间隔，在该沟槽之间的浮动区域位于单元区域中。

公开(公告)号：US20080315248A1

公开(公告)日：2008-12-25

申请号：US11885334

申请日：2007-03-20

申请人： Norihito Tokura ,  Yukio Tsuzuki ,  Kenji Kouno

发明人： Norihito Tokura ,  Yukio Tsuzuki ,  Kenji Kouno

IPC分类号： H01L29/739 ,  G06F17/50

CPC分类号： H01L29/7395 ,  H01L27/0664 ,  H01L29/861

摘要： A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ρ1 and a thickness L1 of the first layer, a resistivity ρ2 and a thickness L2 of the fourth layer, and a half of a minimum width W2 of the second layer on a substrate plane have a relationship of (ρ1/ρ2)×(L1·L2/W22)

摘要翻译： 半导体器件包括：半导体衬底; IGBT单元; 和二极管单元。 衬底包括在第一表面上的第一层，相邻地布置在衬底的第二表面上的第二层和第三层以及在第一层和第二层和第三层之间的第四层。 第一层提供了IGBT单元和二极管单元的漂移层。 第二层提供IGBT单元的集电极层。 第三层提供二极管单元的一个电极连接层。 第一层的电阻率rho1和第一层的厚度L1，第四层的电阻率rho2和厚度L2以及第二层在基板平面上的最小宽度W2的一半具有（rho1 / rho2）× （L1.L2 / W22）<1.6。

公开(公告)号：US20070241394A1

公开(公告)日：2007-10-18

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62.栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US6072240A

公开(公告)日：2000-06-06

申请号：US174171

申请日：1998-10-16

申请人： Tomonori Kimura ,  Norihito Tokura ,  Fumio Ohara ,  Masahito Mizukoshi

发明人： Tomonori Kimura ,  Norihito Tokura ,  Fumio Ohara ,  Masahito Mizukoshi

IPC分类号： H01L25/07 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/072 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

摘要翻译： 即使当半导体芯片具有易受应力的结构时，也能够提高散热性能，实现尺寸的降低，能够迅速地从半导体芯片的两个主面散热。 它包括几个IGBT芯片，每个IGBT芯片在一个主表面上具有集电极电极，在另一个主表面上具有发射极电极和栅极电极，并且两个高导热绝缘基板夹在这些IGBT芯片上，并具有用于接合到IGBT的电极的电极图案 设置在其夹层表面上的芯片，IGBT芯片的电极和高导热绝缘基板的电极图案通过钎焊粘结。

公开(公告)号：US6020600A

公开(公告)日：2000-02-01

申请号：US938805

申请日：1997-09-26

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Kazukuni Hara ,  Hiroo Fuma

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/66068 ,  H01L29/7828 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  Y10S438/981

摘要： A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9. A gate electrode layer 13 is disposed through a gate insulating layer 12 within the trench 9. A source electrode layer 15 is provided on the surface of the p type silicon carbide semiconductor layer 3 and on the surface of the n.sup.+ type source region 6, and a drain electrode layer 16 is provided on the surface of the n.sup.+ type silicon carbide semiconductor substrate 1.

摘要翻译： 提供了具有高阻断电压，低损耗和低阈值电压的碳化硅半导体器件。 n +型碳化硅半导体衬底1，n型碳化硅半导体衬底2和p型碳化硅半导体层3相互层叠在一起。 在p型碳化硅半导体层3的表面的预定区域中形成n +型源极区6，并且形成沟槽9，以延伸穿过n +型源极区6和p型碳化硅半导体层 在n型碳化硅半导体层2的表面上延伸设置有薄膜半导体层（n型或p型）11a，在n +型源极区6，p型碳化硅半导体层3的表面上， 在沟槽9的侧面中的n型碳化硅半导体层2.栅极电极层13通过沟槽9内的栅极绝缘层12设置。源电极层15设置在p型表面上 碳化硅半导体层3和n +型源极区6的表面，以及在n +型碳化硅半导体衬底1的表面上设置漏电极层16。

公开(公告)号：US5973338A

公开(公告)日：1999-10-26

申请号：US947402

申请日：1997-10-08

申请人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

发明人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

摘要翻译： 绝缘栅型双极晶体管（IGBT）在整体结构中包含过电压保护功能和漏极电压固定功能。 杂质浓度ND和n型漏极层（3）的厚度被设定为使得从ap型基极层（7）传播的耗尽区域在低于电压（VDSS）的VDSP下达到p +型漏极层 ），当在源极和漏极之间施加电压时，在IGBT元件内引起雪崩击穿。

公开(公告)号：US5915180A

公开(公告)日：1999-06-22

申请号：US418147

申请日：1995-04-05

申请人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

发明人： Kazukuni Hara ,  Norihito Tokura ,  Takeshi Miyajima ,  Hiroo Fuma ,  Hiroyuki Kano

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  Y10S438/931

摘要： A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench. A gate electrode layer is provided on the surface of the oxide layer, formed by thermal oxidation, within the trench, a source electrode layer is provided on the epitaxial layer and the source region, and a drain electrode layer is provided on the back surface of the semiconductor substrate.

摘要翻译： 具有其厚度的氧化物紫菜的半导体器件可以从沟槽的内表面的一部分变化，并且可以容易地制造，以及其制造方法。 n +型单晶SiC衬底由具有（0001）面取向的碳面作为表面的六方晶系的SiC形成，并且n型外延层和p型外延层依次层叠在衬底上。 在p型外延层内提供n +源极区，并且沟槽延伸穿过源区和外延层进入半导体衬底。 沟槽的侧面几乎垂直于外延层的表面，沟槽的底面具有平行于外延层的表面的平面。 在沟槽的底面上通过热氧化形成的栅极氧化物层的厚度大于沟槽侧面上的栅极氧化物层的厚度。 在氧化层形成的氧化层的表面上，在沟槽内设置栅极电极层，在外延层和源极区域设置有源电极层，在其背面设有漏电极层 半导体衬底。