公开(公告)号：US11583171B2

公开(公告)日：2023-02-21

申请号：US16548753

申请日：2019-08-22

Applicant: OmniVision Technologies, Inc.

Inventor： Teng-Sheng Chen ,  Chien-Chan Yeh ,  Cheng-Fang Chiu ,  Wei-Feng Lin

IPC: H05K1/11 ,  H05K3/46 ,  A61B1/005

Abstract: A surface-mount device platform includes a surface-mounting region, a connection region, and a bendable region therebetween, each including a respective part of a base substrate. The base substrate includes electrically-conductive layers interspersed with electrically-insulating build-up layers. Each of the surface-mounting region, the connection region, and the bendable region spans between a bottom substrate-surface and a top substrate-surface of the base substrate. The surface-mounting region further includes an electrically-insulating first top rigid-layer, and device bond-pads exposed on a top surface of the first top rigid-layer facing away from the top substrate-surface in the surface-mounting region. The connection region further includes an electrically-insulating second top rigid-layer and a plurality of connector bond-pads each exposed on a top surface of the second top rigid-layer facing away from the top substrate-surface in the connection region, and electrically connected to a respective device bond-pad via at least one of the electrically conductive layers.

公开(公告)号：US20220077210A1

公开(公告)日：2022-03-10

申请号：US17530358

申请日：2021-11-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Wei-Feng Lin ,  Ying-Chih Kuo ,  Ying Chung

IPC: H01L27/146

Abstract: A method of image sensor package fabrication includes forming a recess in a transparent substrate, depositing conductive traces in the recess, inserting an image sensor in the recess so that the image sensor is positioned in the recess to receive light through the transparent substrate, and inserting a circuit board in the recess so that the image sensor is positioned between the transparent substrate and the circuit board.

公开(公告)号：US10985149B2

公开(公告)日：2021-04-20

申请号：US16248125

申请日：2019-01-15

Applicant: Omnivision Technologies, Inc.

Inventor： Chien Chan Yeh ,  Ying-Chih Kuo ,  Wei-Feng Lin

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56

Abstract: A semiconductor device package includes a transparent substrate, a photo detector and a first conductive layer. The transparent substrate has a first surface and a first cavity underneath the first surface. The photo detector is disposed within the first cavity. The photo detector has a sensing area facing toward a bottom surface of the first cavity of the transparent substrate. The first conductive layer is disposed over the transparent substrate and electrically connected to the photo detector.

公开(公告)号：US20200243384A1

公开(公告)日：2020-07-30

申请号：US16257223

申请日：2019-01-25

Applicant: OmniVision Technologies, Inc.

Inventor： Wei-Feng Lin ,  Chi-Chih Huang

IPC: H01L21/768 ,  H01L23/544 ,  H01L23/00 ,  H01L27/146

Abstract: A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern formed using laser marking on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the at least one code pattern is visible from a backside of the chip, the at least one code pattern represents a binary number having four bits; and the binary number represents a decimal number to represent a tracing number of the chip.

公开(公告)号：US10082651B2

公开(公告)日：2018-09-25

申请号：US15095585

申请日：2016-04-11

Applicant: OmniVision Technologies, Inc.

Inventor： Teng-Sheng Chen ,  Jau-Jan Deng ,  Wei-Feng Lin

IPC: H04N5/225 ,  G02B13/00 ,  G01J1/02 ,  H01L31/0203

CPC classification number: G02B13/0085 ,  G01J1/0204 ,  G01J1/0403 ,  G01J1/0411 ,  G01J1/4228 ,  H04N5/2252 ,  H04N5/2253 ,  H04N5/2254

Abstract: In an embodiment, a slim imager is disclosed. The slim imager includes a substrate including an aperture, an image sensor, and an optics unit. The image sensor is on a bottom side of the substrate, spans the aperture, and has an aperture-facing top surface. The optics unit is on a top side of the substrate, spans the aperture, and includes a transmissive optical element having an aperture-facing bottom surface. A volume partially bound by the aperture-facing top surface and the aperture-facing bottom surface has a refractive index less than 1.01 at visible wavelengths.

公开(公告)号：US20180182797A1

公开(公告)日：2018-06-28

申请号：US15899900

申请日：2018-02-20

Applicant: OmniVision Technologies, Inc.

Inventor： Wei-Feng Lin ,  Chi-Chih Huang ,  En-Chi Li

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469

Abstract: A method of image sensor package fabrication includes forming a cavity in a ceramic substrate, and placing an image sensor in the cavity in the ceramic substrate. An image sensor processor is also placed in the cavity in the ceramic substrate, and the image sensor and the image sensor processor are wire bonded to electrical contacts. Glue is deposited on the ceramic substrate, and a glass layer is placed on the glue to adhere the glass layer to the ceramic substrate. The image sensor processor and the image sensor are disposed in the cavity between the glass layer and the ceramic substrate.

公开(公告)号：US20180082937A1

公开(公告)日：2018-03-22

申请号：US15268169

申请日：2016-09-16

Applicant: OmniVision Technologies, Inc.

Inventor： Chi-Kuei Lee ,  Ying Chung ,  Ying-Chih Kuo ,  Wei-Feng Lin

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/02274 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0401

Abstract: A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed over the redistribution conductors of the redistribution layer and in contact with the passivation layer. The passivation layer and the cap layer have one or more compatibilities that provide sufficient adhesion between those two layers to prevent metal migration from the conductors of the redistribution layer between the interfaces of the passivation and cap layers. In one embodiment, the passivation and cap layers are each formed from an inorganic oxide (e.g., SiO2) using a process (e.g., PECVD) that provides substantially-uniform step coverage by the cap layer in trench and via regions of underlying circuitry. The invention increases the reliability of the microchip, because it eliminates metal migration, and the electrical shorting caused therefrom, in the redistribution layer.

公开(公告)号：US09922922B1

公开(公告)日：2018-03-20

申请号：US15268169

申请日：2016-09-16

Applicant: OmniVision Technologies, Inc.

Inventor： Chi-Kuei Lee ,  Ying Chung ,  Ying-Chih Kuo ,  Wei-Feng Lin

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/02274 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/0401

Abstract: A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed over the redistribution conductors of the redistribution layer and in contact with the passivation layer. The passivation layer and the cap layer have one or more compatibilities that provide sufficient adhesion between those two layers to prevent metal migration from the conductors of the redistribution layer between the interfaces of the passivation and cap layers. In one embodiment, the passivation and cap layers are each formed from an inorganic oxide (e.g., SiO2) using a process (e.g., PECVD) that provides substantially-uniform step coverage by the cap layer in trench and via regions of underlying circuitry. The invention increases the reliability of the microchip, because it eliminates metal migration, and the electrical shorting caused therefrom, in the redistribution layer.

公开(公告)号：US09812478B2

公开(公告)日：2017-11-07

申请号：US14639610

申请日：2015-03-05

Applicant: OmniVision Technologies, Inc.

Inventor： Chun-Sheng Fan ,  Wei-Feng Lin

IPC: H01L31/0216 ,  H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14698 ,  H01L2224/11 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

Abstract: An aerogel-encapsulated image sensor includes a device die with an image sensor fabricated thereon and an aerogel layer that encapsulates the image sensor. A method for encapsulating image sensor pixel arrays of respective bare image sensors formed on a sensor array sheet may include injecting an uncured aerogel portion on each image sensor pixel array, and curing each uncured aerogel portion. The step of curing may include at least one of (a) super-critical drying, (b) surface-modification drying, and (c) pinhole drying an uncured aerogel portion. The method may further include singulating the sensor array sheet into a plurality of aerogel-encapsulated image sensors. A method for encapsulating image sensor pixel arrays of respective bare image sensors on a device wafer may include forming an aerogel layer on each bare image sensor. The step of forming may include at least one of spin-coating, dip-coating, and spray-coating the aerogel layer.

公开(公告)号：US20170294471A1

公开(公告)日：2017-10-12

申请号：US15096136

申请日：2016-04-11

Applicant: OmniVision Technologies, Inc.

Inventor： Yumei Su ,  Chi-Chih Huang ,  Wei-Feng Lin

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  H01L27/14687

Abstract: A trenched device wafer includes a device substrate layer having a top surface; a plurality of devices in the device substrate layer, and a trench in the top surface. The trench extends into the device substrate layer, and is located between a pair of adjacent devices of the plurality of devices. A method for forming a device die from a device wafer includes forming a trench in a top surface of the device wafer between two adjacent devices of the device wafer. The trench has a bottom surface located (a) at a first depth beneath the top surface and (b) at a first height above a wafer bottom surface. The method also includes, after forming the trench, decreasing a thickness of the device wafer, between the two adjacent devices, to a thickness less than the first height.