公开(公告)号：US07904641B2

公开(公告)日：2011-03-08

申请号：US12123195

申请日：2008-05-19

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

Abstract translation: 一种处理器系统，包括：通过内部总线连接的处理器和控制器核; 以及经由外部总线连接到处理器的多个同步存储器芯片; 所述控制器核心包括通过来自所述处理器核心的地址信号选择的模式寄存器，并且通过来自所述处理器核心的数据信号写入信息以选择所述多个同步存储器芯片的操作模式;以及控制单元，用于规定所述操作 模式基于写入模式寄存器中的信息而发送到多个同步存储器芯片，其中控制器核心基于写入模式寄存器中的信息或从处理器核心的存取地址信号向多个同步信号输出模式设置信号 选择性地通过外部总线的存储器芯片; 并且其中所述时钟信号被共同地提供给所述多个同步存储器芯片。

公开(公告)号：US20070061537A1

公开(公告)日：2007-03-15

申请号：US11598661

申请日：2006-11-14

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F13/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.

Abstract translation: 芯片包括：微处理器; 耦合到所述微处理器的控制单元; 以及用于耦合同步动态存储器的接口节点; 其中所述控制单元产生命令信息，并且所述接口节点与时钟信号同步地将所述命令信息输出到所述同步动态存储器，其中所述命令信息包括将模式信息设置到所述同步动态存储器中的模式寄存器的模式寄存器设置功能 并且其中所述控制单元将所述模式信息输出到所述同步动态存储器的地址信号输入端子。

公开(公告)号：US07023757B2

公开(公告)日：2006-04-04

申请号：US10373042

申请日：2003-02-26

Applicant: Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

Inventor： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC: G11C8/00 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

公开(公告)号：US07003651B2

公开(公告)日：2006-02-21

申请号：US10017198

申请日：2001-12-18

Applicant: Yuki Kondoh ,  Osamu Nishii

Inventor： Yuki Kondoh ,  Osamu Nishii

IPC: G06F9/32

CPC classification number: G06F9/382 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3802

Abstract: The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

公开(公告)号：US06715090B1

公开(公告)日：2004-03-30

申请号：US09308488

申请日：1999-05-20

Applicant: Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

Inventor： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC: G06F130

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US06424560B1

公开(公告)日：2002-07-23

申请号：US09824232

申请日：2001-04-03

Applicant: Osamu Nishii ,  Motonobu Tonomura ,  Takanobu Tsunoda

Inventor： Osamu Nishii ,  Motonobu Tonomura ,  Takanobu Tsunoda

IPC: G11C1100

Abstract: A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is disclosed. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

公开(公告)号：US06292867B1

公开(公告)日：2001-09-18

申请号：US09641913

申请日：2000-08-21

Applicant: Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

Inventor： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

IPC: G06F1202

CPC classification number: G06F12/0215 ,  G06F13/1631

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract translation: 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。

公开(公告)号：US6078986A

公开(公告)日：2000-06-20

申请号：US689730

申请日：1996-08-13

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F15/78 ,  G11C7/10 ,  G11C8/12 ,  G11C8/18 ,  H04N7/26 ,  H04N7/50 ,  G06F12/06

CPC classification number: G11C8/18 ,  G06F13/4217 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

公开(公告)号：US5873122A

公开(公告)日：1999-02-16

申请号：US815600

申请日：1997-03-12

Applicant: Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

Inventor： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0215 ,  G06F13/1631

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract translation: 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。

公开(公告)号：US5557760A

公开(公告)日：1996-09-17

申请号：US117681

申请日：1993-09-08

Applicant: Osamu Nishii ,  Takashi Inagawa ,  Makoto Hanawa ,  Hiroshi Takeda

Inventor： Osamu Nishii ,  Takashi Inagawa ,  Makoto Hanawa ,  Hiroshi Takeda

IPC: G06F12/08 ,  G06F13/40 ,  G06F13/20

CPC classification number: G06F12/0893 ,  G06F13/4072

Abstract: A processor for use in a data processing system with a cache RAM and main memory has a control pin for deactivating the driving of the data bus without deactivating that of the address bus during a write cycle. This capability is useful during a cache storing operation following a miss for performing a write operation without the requirement of additional address storing circuitry. In particular, during a cache storing operation, the processor can drive the address bus while control of the data bus by the processor is floated. Then, the data in main memory can be put on the data bus and transferred into the cache memory. Once the data is transferred to the cache memory, the original write operation can be completed.

Abstract translation: 用于具有高速缓存RAM和主存储器的数据处理系统中的处理器具有控制引脚，用于在写周期期间停用数据总线的驱动而不停用地址总线的驱动。 在无需附加地址存储电路的执行写入操作之后的高速缓存存储操作期间，该能力是有用的。 特别地，在高速缓存存储操作期间，处理器可以驱动地址总线，同时处理器的数据总线的控制是浮动的。 然后，主存储器中的数据可以放在数据总线上并传输到高速缓存中。 一旦将数据传输到高速缓冲存储器，可以完成原始写入操作。