公开(公告)号：US08455923B2

公开(公告)日：2013-06-04

申请号：US13135220

申请日：2011-06-29

申请人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

IPC分类号： H01L27/118

CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825 ,  H01L29/7881

摘要： An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

摘要翻译： 由非易失性存储器阵列电路，逻辑电路和线性模拟电路形成的集成电路形成在基板上。 非易失性存储器阵列电路，逻辑电路和线性模拟电路由通过浅沟槽隔离形成的隔离区隔开。 非易失性存储器阵列电路形成为三重阱结构。 非易失性存储器阵列电路是由至少两个串联连接的浮栅晶体管形成的基于NAND的NOR存储器电路，使得浮栅晶体管中的至少一个用作选择栅极晶体管，以防止漏电流通过电荷保持晶体管， 电荷保持晶体管不被选择用于读取。 基于NAND的NOR存储器电路的每列与一个位线和一个源极线相关联并连接到一个位线和一个源极线。

公开(公告)号：US08345481B2

公开(公告)日：2013-01-01

申请号：US13317678

申请日：2011-10-25

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/30 ,  G11C2211/5641 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  Y10T29/41

摘要： A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

摘要翻译： NOR闪存非易失性存储器或可重构逻辑器件具有NOR闪存非易失性存储器电路阵列，其包括串联连接在NAND串中的电荷保持晶体管，使得至少一个电荷保持晶体管用作选择栅极晶体管，以防止漏电流通过 当电荷保持晶体管未被选择用于读取时的电荷保持晶体管。 最上面的电荷保持晶体管的漏极连接到与电荷保持晶体管平行的位线，并且最下面的电荷保持晶体管的源极连接到源极线并且平行于位线。 电荷保持晶体管通过Fowler-Nordheim隧道工艺进行编程和擦除。

公开(公告)号：US08274829B2

公开(公告)日：2012-09-25

申请号：US12455936

申请日：2009-06-09

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C11/34 ,  G11C11/4193

CPC分类号： G11C8/12 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16

摘要： An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing operational disturbances and providing bias operating conditions to prevent gate to source breakdown in peripheral devices. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing operational disturbances and preventing gate to source breakdown in peripheral devices.

摘要翻译： 用于操作NOR连接的闪存非易失性存储器单元的阵列的装置和方法以页，块，扇区或整个阵列的增量擦除阵列，同时最小化操作干扰并提供偏置操作条件以防止外围设备中的门源故障 。 该装置具有行解码器电路和源解码器电路，用于选择非易失性存储单元，以提供用于读取，编程，验证和擦除所选择的非易失性存储单元的偏置条件，同时最小化操作干扰并防止门外围设备中的故障。

公开(公告)号：US20120072647A1

公开(公告)日：2012-03-22

申请号：US13200141

申请日：2011-09-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G06F12/00 ,  H05K3/00

CPC分类号： G06F12/0638 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C11/005 ,  G11C16/32 ,  G11C2216/30 ,  Y02D10/13 ,  Y10T29/49124

摘要： A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

摘要翻译： 半导体芯片在一个存储器芯片中包含四种不同的存储器类型，EEPROM，NAND闪存，NOR闪存和SRAM以及多个主要的串行/并行接口，例如I2C，SPI，SDI和SQI。 内存芯片具有写时同时写入和读写操作以及读写同时传输和写时同时传输操作。 存储器芯片提供八个引脚，其中两个用于供电，最多四个引脚没有连接用于特定接口，并且使用新颖的统一的非易失性存储器设计，允许集成在一起的上述存储器类型集成在同一半导体存储器芯片 。

公开(公告)号：US20110157974A1

公开(公告)日：2011-06-30

申请号：US12930022

申请日：2010-12-23

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/06 ,  G11C16/04 ,  H01L21/82

CPC分类号： G11C16/10 ,  G11C16/0433 ,  H01L27/11521

摘要： Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with the bit line and connected to a source of a floating gate transistor of each of the two-transistor FLOTOX EEPROM cells. In a program operation, the bit lines are connected to a very large programming voltage level and the source lines are connected to a punch through inhibit voltage level. The punch through inhibit voltage level is approximately one half the very large programming voltage level. The lower drain-to-source voltage level permits the select transistor and the floating gate transistor to have smaller channel lengths and therefore a lower drain-to-source breakdown voltage.

摘要翻译： 收集双晶体管FLOTOX EEPROM单元以形成诸如字节的可变单元。 每个双晶体管FLOTOX EEPROM单元具有连接到每个双晶体管FLOTOX EEPROM单元的选择晶体管的漏极的位线和与位线并联放置并连接到浮置源的源极线 两个晶体管FLOTOX EEPROM单元的栅极晶体管。 在编程操作中，位线连接到非常大的编程电压电平，并且源极线通过禁止电压电平连接到冲头。 通过禁止电压电平的冲击大约是非常大的编程电压电平的一半。 较低的漏极 - 源极电压电平允许选择晶体管和浮动栅极晶体管具有较小的沟道长度，因此具有较低的漏极 - 源极击穿电压。

公开(公告)号：US20110096609A1

公开(公告)日：2011-04-28

申请号：US12925489

申请日：2010-10-22

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L27/088

CPC分类号： H01L27/11568 ,  G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11521

摘要： A nonvolatile memory array has nonvolatile memory cells arranged in rows and columns where each column has a bit line and source line associated with and in parallel with the nonvolatile memory cells. In programming the nonvolatile memory cell, approximately equal program voltage levels are applied to a drain and a source of a selected charge retaining transistor such that the difference in the voltage between the drain and the source of the selected charge retaining transistor is less than a drain to source breakdown voltage of the selected charge retaining transistor to prevent drain-to-source punch through. In programming or erasing the nonvolatile memory cell a control gate and a bulk program voltage level is applied to a control gate and bulk such that the magnitude of the control gate and bulk program voltage levels is less than a breakdown voltage level of peripheral circuitry.

摘要翻译： 非易失性存储器阵列具有排列成行和列的非易失性存储单元，其中每列具有与非易失性存储单元相关联并与其并行的位线和源极线。 在对非易失性存储单元进行编程时，将大致相同的编程电压电平施加到所选择的电荷保持晶体管的漏极和源极，使得所选择的电荷保持晶体管的漏极和源极之间的电压差小于漏极 以引发所选择的电荷保持晶体管的击穿电压，以防止漏极到源极穿通。 在编程或擦除非易失性存储单元时，控制栅极和大容量编程电压电平被施加到控制栅极和体积，使得控制栅极和体编程电压电平的幅度小于外围电路的击穿电压电平。

公开(公告)号：US20100124118A1

公开(公告)日：2010-05-20

申请号：US12291913

申请日：2008-11-14

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： G11C11/5621 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L29/7923

摘要： A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the threshold voltage adjustable select transistors has its threshold voltage level adjusted to a first threshold voltage level and a second of the threshold voltage adjustable select transistors adjusted to a second threshold voltage level. The pair of serially connected threshold voltage adjustable select transistors is connected to a first of two associated bit lines. The NAND nonvolatile memory strings further is connected to a pair of serially connected threshold voltage adjustable bottom select transistors that is connected to the second associated bit line.

摘要翻译： 连接到双极电荷捕获非易失性存储器单元的组的NAND系列的顶部和可选地连接到底部的具有串联连接的阈值电压可调选择晶体管的非易失性存储器结构，用于控制NAND系列串与 关联位线。 阈值电压可调选择晶体管中的第一个阈值电压电平被调整到第一阈值电压电平，而阈值电压可调选择晶体管中的第二阈值电压调整到第二阈值电压电平。 一对串联连接的阈值电压可调选择晶体管连接到两个相关位线中的第一个。 NAND非易失性存储器串还连接到连接到第二关联位线的一对串联连接的阈值电压可调底部选择晶体管。

公开(公告)号：US20090190402A1

公开(公告)日：2009-07-30

申请号：US12319241

申请日：2009-01-05

申请人： Fu-Chang Hsu ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Peter Wung Lee

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/00 ,  G11C5/14 ,  H01S4/00

CPC分类号： G11C14/00 ,  G11C14/0063 ,  Y10T29/49002

摘要： A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a read voltage level and erasing to a second data level, the threshold voltage of the FLOTOX EEPROM transistor is brought to an erased voltage level less than the read voltage level. The nonvolatile SRAM array provides for restoring data to an SRAM cell from a FLOTOX EEPROM memory cell(s) at a power initiation and storing data to the FLOTOX EEPROM memory cell(s) to the SRAM cell at power termination. A power detection circuit for providing signals indicating power initiation and power termination to instigate restoration and storing of data between an SRAM cell and a FLOTOX EEPROM cell(s).

摘要翻译： 非易失性SRAM电路具有连接到SRAM单元的数据存储端的SRAM单元和一个或两个FLOTOX EEPROM单元。 在编程到第一数据电平时，FLOTOX EEPROM晶体管的阈值电压达到大于读取电压电平并被擦除到第二数据电平的编程电压电平，FLOTOX EEPROM晶体管的阈值电压被擦除 电压电平小于读取电压电平。 非易失性SRAM阵列用于在功率发生时从FLOTOX EEPROM存储单元向SRAM单元恢复数据，并在断电时将数据存储到SRAM单元中的FLOTOX EEPROM存储单元。 一种功率检测电路，用于提供指示功率启动和功率终止的信号，以在SRAM单元和FLOTOX EEPROM单元之间启动数据的恢复和存储。

公开(公告)号：US06240027B1

公开(公告)日：2001-05-29

申请号：US09693503

申请日：2000-10-23

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Mike Hsinyih Chen

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Mike Hsinyih Chen

IPC分类号： G11C700

CPC分类号： G11C16/102 ,  G11C5/145 ,  G11C16/16

摘要： In this invention external high voltages are connected to a chip containing a flash memory that are connected to selected cells to be erased. Internal pump circuits contained on the chip are turned off while the external voltages are used. The external voltages, a high negative voltage and a high positive voltage, are connected to gates and sources respectively of selected cells to be erased by a voltage control module. The external voltages are used during manufacture during program/erase operations to perform the erase function efficiently. The internal high voltage pump circuits are used to erase flash memory cells after being assembled on a circuit board by a user. Two level shifter circuits are disclosed that form a part of the voltage control module. The level shifter circuits apply voltages to the flash memory cells and provide voltages that select and deselect the cells for erasure.

摘要翻译： 在本发明中，外部高电压连接到包含连接到要擦除的所选单元的闪速存储器的芯片。 使用外部电压时，芯片上包含的内部泵电路关闭。 外部电压，高负电压和高正电压分别连接到要由电压控制模块擦除的所选单元的门和源。 在编程/擦除操作期间在制造期间使用外部电压以有效地执行擦除功能。 内部高压泵电路用于在由用户组装在电路板上之后擦除闪存单元。 公开了形成电压控制模块的一部分的两个电平移位器电路。 电平移位器电路向闪存单元施加电压并提供选择和取消选择单元用于擦除的电压。

公开(公告)号：US6160737A

公开(公告)日：2000-12-12

申请号：US369761

申请日：1999-07-06

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter Wung Lee

IPC分类号： G11C16/04 ,  G11C16/12 ,  G11C16/16

CPC分类号： G11C16/12 ,  G11C16/0416 ,  G11C16/16

摘要： Bias conditions for improving the efficiency of repairing, programming and erasing the threshold voltages of non-volatile memory devices. A positive voltage is applied to the source region of a non-volatile memory cell. The control gate of the memory cell is applied with another positive voltage higher the voltage at the source region. The difference between the two voltages is proportional to the desired final threshold voltage. The drain region can be applied with a positive voltage directly from the power supply of the memory device. A negative voltage is applied to the bulk of the memory device so that a large electric field across the control gate and the bulk can induce hot-electron injection. By selecting the proper voltage level at the control gate, the method can be used for the repair, program or erase operation of memory devices.

摘要翻译： 用于提高修复，编程和擦除非易失性存储器件的阈值电压效率的偏置条件。 正电压被施加到非易失性存储单元的源极区域。 存储单元的控制栅极被施加在源极区域上的电压更高的另一个正电压。 两个电压之间的差异与期望的最终阈值电压成比例。 漏极区域可以直接从存储器件的电源施加正电压。 负电压被施加到存储器件的大部分，使得跨越控制栅极和本体的大电场可以引起热电子注入。 通过在控制门选择适当的电压电平，该方法可用于存储器件的修复，编程或擦除操作。