公开(公告)号：US09959912B2

公开(公告)日：2018-05-01

申请号：US15013897

申请日：2016-02-02

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  Sei Seung Yoon ,  Keejong Kim

IPC: G11C7/02 ,  G11C7/00 ,  G11C7/08 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/026 ,  G11C29/14 ,  G11C29/50012

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

公开(公告)号：US09748003B2

公开(公告)日：2017-08-29

申请号：US14485379

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Robert Henry Hoem

IPC: G11C8/12 ,  G11C29/00 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C8/10

CPC classification number: G11C29/781 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  G11C29/802 ,  G11C29/806

Abstract: A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.

公开(公告)号：US09627041B1

公开(公告)日：2017-04-18

申请号：US15010385

申请日：2016-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  Sei Seung Yoon ,  Keejong Kim

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/417 ,  G11C11/418 ,  G11C29/12005 ,  G11C2029/1202

Abstract: A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.

公开(公告)号：US20160276005A1

公开(公告)日：2016-09-22

申请号：US15070963

申请日：2016-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

IPC: G11C8/08 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

Abstract translation: 提供了一种存储器，其包括行解码器，其将地址解码为用于从多个字线选择要断言的字线的多个解码信号。 每个字线通过处理解码信号的解码器电平转换器驱动。 每个解码器电平转换器对应于解码信号的唯一组合。 行解码器处于逻辑功率域，使得解码信号被断言为逻辑电源电压。 当解码器电平移位器的解码信号的唯一组合由行解码器确定时，解码器电平转换器用存储器电源域的存储器电源电压驱动相应的字线。

公开(公告)号：US20160078969A1

公开(公告)日：2016-03-17

申请号：US14485379

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Robert Henry Hoem

IPC: G11C29/00 ,  G11C17/18 ,  G11C11/418 ,  G11C17/16

CPC classification number: G11C29/781 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  G11C29/802 ,  G11C29/806

Abstract: A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.

Abstract translation: 可以提供为诸如SRAM之类的多个嵌入存储器提供冗余的系统。 系统可以包括一个或多个解码器，每个解码器能够解码选择地址以识别嵌入存储器中的有缺陷的一个。

公开(公告)号：US09071239B2

公开(公告)日：2015-06-30

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00 ,  G11C7/10 ,  G11C7/02

CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

公开(公告)号：US11837313B2

公开(公告)日：2023-12-05

申请号：US17517386

申请日：2021-11-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: G11C29/00 ,  G11C29/50 ,  G11C8/08 ,  H03K19/0175 ,  H03K19/20

CPC classification number: G11C29/50016 ,  G11C8/08 ,  G11C2029/5004 ,  H03K19/017509 ,  H03K19/20

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

公开(公告)号：US11615837B2

公开(公告)日：2023-03-28

申请号：US17028965

申请日：2020-09-22

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Arun Babu Pallerla ,  Chulmin Jung

IPC: G11C11/419 ,  G11C11/413 ,  H03K19/20

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

公开(公告)号：US11170845B1

公开(公告)日：2021-11-09

申请号：US16928658

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Derek Yang ,  Chulmin Jung ,  Changho Jung

IPC: G11C8/08 ,  G11C11/418

Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

公开(公告)号：US10770132B1

公开(公告)日：2020-09-08

申请号：US16523768

申请日：2019-07-26

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Arun Babu Pallerla ,  Chulmin Jung

IPC: G11C11/418 ,  G11C11/419

Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a previous row address to determine whether a read operation is a normal read operation or a burst mode read operation.