公开(公告)号：US09461094B2

公开(公告)日：2016-10-04

申请号：US14334554

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen ,  Yu Lu ,  Kangho Lee ,  Seung Hyuk Kang

IPC: G11C11/00 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L27/224 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/73 ,  H01L27/228 ,  H01L43/08

Abstract: An MRAM cell may include a magnetic tunneling junction (MTJ). The MTJ includes a pin layer, a barrier layer, a free layer, and a capping layer. The MRAM cell further includes a bidirectional diode selector, directly coupled to an electrode of the MTJ, to enable access to the MTJ.

Abstract translation: MRAM单元可以包括磁隧道结（MTJ）。 MTJ包括针层，阻挡层，自由层和覆盖层。 MRAM单元还包括直接耦合到MTJ的电极的双向二极管选择器，以使得能够访问MTJ。

公开(公告)号：US20160254318A1

公开(公告)日：2016-09-01

申请号：US14856316

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic random access memory (MRAM) bit cells employing source lines and/or bit lines disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.

Abstract translation: 公开了使用设置在多个堆叠金属层中的源极线和/或位线的磁性随机存取存储器（MRAM）位单元，以减少MRAM位单元电阻。 还公开了相关方法和系统。 在本文公开的方面，MRAM位单元被提供在存储器阵列中。 在集成电路（IC）中制造MRAM位单元，源极线和/或位线由设置在半导体层上方的多个堆叠金属层形成，以减小源极线的电阻。 以这种方式，如果IC中的节点尺寸按比例缩小，则可以维持或减小源极线和/或位线的电阻，以避免产生用于MRAM位的写入操作的写入电流的驱动电压的增加 细胞。

公开(公告)号：US20160172456A1

公开(公告)日：2016-06-16

申请号：US14567925

申请日：2014-12-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Bin Yang ,  Jun Yuan ,  Yu Lu

IPC: H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.

Abstract translation: 半导体器件包括具有金属栅极，源极和漏极的晶体管。 半导体器件还包括位于晶体管的金属栅极上方的高电阻金属蚀刻停止层。 半导体器件还包括形成在高电阻金属蚀刻停止层上的金属层。 金属层位于晶体管的源极或晶体管的漏极中的至少一个的上方。

公开(公告)号：US20160049185A1

公开(公告)日：2016-02-18

申请号：US14460626

申请日：2014-08-15

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1695 ,  G11C2213/78 ,  H01L27/228

Abstract: An apparatus includes a first magnetic tunnel junction (MTJ) device of a differential MTJ pair. The apparatus further includes a second MTJ device of the differential MTJ pair. The first MTJ device includes a sense layer having a high coercivity portion.

Abstract translation: 一种装置包括差分MTJ对的第一磁隧道结（MTJ）装置。 该装置还包括差分MTJ对的第二MTJ装置。 第一MTJ装置包括具有高矫顽力部分的感测层。

公开(公告)号：US20150340593A1

公开(公告)日：2015-11-26

申请号：US14286518

申请日：2014-05-23

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Chando Park ,  Wei-Chuan Chen

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a spacer on an exposed side portion of the MTJ device. The method further includes forming an etch-resistant protective coating associated with the MTJ device. The etch-resistant protective coating provides greater etch resistance than the spacer.

Abstract translation: 形成磁性隧道结（MTJ）装置的方法包括在MTJ装置的暴露侧部分上形成间隔物。 该方法还包括形成与MTJ装置相关联的耐蚀刻保护涂层。 耐蚀刻保护涂层比间隔物提供更大的耐蚀刻性。

公开(公告)号：US09142762B1

公开(公告)日：2015-09-22

申请号：US14229427

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Kangho Lee ,  Wei-Chuan Chen ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。