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公开(公告)号：US09979295B2
公开(公告)日：2018-05-22
申请号：US15477579
申请日：2017-04-03
Applicant: Qorvo US, Inc.
Inventor： Michael R. Kay , Manbir Singh Nag
CPC classification number: H02M3/1582 , H02M3/07 , H02M3/1584 , H02M2001/0003 , H02M2001/0045 , H02M2001/4291 , H02M2003/1586 , H03F3/38
Abstract: A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.
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公开(公告)号：US20180048276A1
公开(公告)日：2018-02-15
申请号：US15459449
申请日：2017-03-15
Applicant: Qorvo US, Inc.
Inventor： Nadim Khlat , Michael R. Kay
CPC classification number: H03G3/3036 , H03F1/0227 , H03F1/025 , H03F3/19 , H03F3/195 , H03F3/45475 , H03F2200/102 , H03F2200/351 , H03F2200/451 , H03G3/3042
Abstract: A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in low-resource block (RB) mode and high-RB mode. The multi-mode ET amplifier circuit includes an ET amplifier(s) to amplify a radio frequency (RF) signal(s) to an amplified voltage, low-RB switcher circuitry to generate a direct current (DC) current, and high-RB switcher circuitry to generate an alternating current (AC) current. The amplified voltage, the DC current, and the AC current collectively cause the RF signal to be transmitted at a determined power. A control circuit(s) activates the high-RB switcher circuitry in the high-RB mode to provide the AC current, thus minimizing AC current sourced from the ET amplifier(s). As a result, it is possible to improve efficiency of the ET amplifier(s) and the multi-mode ET amplifier circuit in the high-RB mode and the low-RB mode.
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公开(公告)号：US20170207705A1
公开(公告)日：2017-07-20
申请号：US15477579
申请日：2017-04-03
Applicant: Qorvo US, Inc.
Inventor： Michael R. Kay , Manbir Singh Nag
CPC classification number: H02M3/1582 , H02M3/07 , H02M3/1584 , H02M2001/0003 , H02M2001/0045 , H02M2001/4291 , H02M2003/1586 , H03F3/38
Abstract: A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.
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公开(公告)号：US20170179888A1
公开(公告)日：2017-06-22
申请号：US15382773
申请日：2016-12-19
Applicant: Qorvo US, Inc.
Inventor： Manbir Singh Nag , Michael R. Kay , Philippe Gorisse , Nadim Khlat
CPC classification number: H03F1/0222 , H03F3/193 , H03F3/245 , H03F2200/102 , H03F2200/105 , H03F2200/451 , H03F2200/507 , H04W52/52
Abstract: A PA power supply, which includes a first ET power supply, power supply control circuitry, a first PMOS switching element, and a second PMOS switching element, is disclosed. During a first operating mode, the power supply control circuitry selects an OFF state of the first PMOS switching element, selects an ON state of the second PMOS switching element, and adjusts a voltage of a first switch control signal to maintain the OFF state of the first PMOS switching element using a voltage at a source of the first PMOS switching element and a voltage at a drain of the first PMOS switching element; the PA power supply provides a first PA power supply signal; and the first ET power supply provides a first ET power supply signal, such that the first PA power supply signal is based on the first ET power supply signal.
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公开(公告)号：US12301184B2
公开(公告)日：2025-05-13
申请号：US18203197
申请日：2023-05-30
Applicant: Qorvo US, Inc.
Inventor： Nadim Khlat , Michael R. Kay
Abstract: An average power tracking (APT) power management circuit is provided. The APT power management circuit is configured to generate a first APT voltage(s) for a first power amplifier(s) and a second APT voltage(s) for a second power amplifier(s). The APT power management circuit further includes a pair of switcher circuits that can generate a pair of reference voltages. Depending on various operating scenarios of the APT power management circuit, it is possible to selectively output any of the reference voltages as any one or more of the first APT voltage(s) and the second APT voltage(s). As such, it is possible to flexibly configure the APT power management circuit to support the various operating scenarios based on a minimum possible number of the switcher circuits, thus helping to reduce footprint and cost of the APT power management circuit.
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Patent Agency Ranking
公开(公告)号：US20240356545A1
公开(公告)日：2024-10-24
申请号：US18627676
申请日：2024-04-05
Applicant: Qorvo US, Inc.
Inventor： Baker Scott , Douglas R. Farrenkopf , Nadim Khlat , George Maxim , Christopher T. Brown , Michael R. Kay
IPC: H03K17/687 , H02M3/07 , H02M3/158 , H03K17/06
CPC classification number: H03K17/6872 , H02M3/07 , H02M3/1582 , H03K17/063
Abstract: A switching circuit for power management circuits and front-end modules (FEMs) is disclosed. In one aspect, a switching circuit is made from N-type field effect transistors (NFETs) that couple directly to charge pumps associated with converters in the power management circuits. The charge pumps provide a desired gate bias for the NFETs to allow for low loss across the source drain of the NFET. By providing such an NFET-based switching circuit, different FEMs may be coupled to different converters across a wide voltage range. NFETs are smaller than comparable P-type FETs (PFETs) and require less control circuitry. Accordingly, space and cost may be reduced while still providing desired performance across a desired voltage range.
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公开(公告)号：US11736076B2
公开(公告)日：2023-08-22
申请号：US17217594
申请日：2021-03-30
Applicant: Qorvo US, Inc.
Inventor： Nadim Khlat , Michael R. Kay
CPC classification number: H03F3/245 , H03F1/0233 , H03F3/195 , H03F2200/105 , H03F2200/451
Abstract: An average power tracking (APT) power management circuit is provided. The APT power management circuit is configured to generate a first APT voltage(s) for a first power amplifier(s) and a second APT voltage(s) for a second power amplifier(s). The APT power management circuit further includes a pair of switcher circuits that can generate a pair of reference voltages. Depending on various operating scenarios of the APT power management circuit, it is possible to selectively output any of the reference voltages as any one or more of the first APT voltage(s) and the second APT voltage(s). As such, it is possible to flexibly configure the APT power management circuit to support the various operating scenarios based on a minimum possible number of the switcher circuits, thus helping to reduce footprint and cost of the APT power management circuit.
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公开(公告)号：US20230238927A1
公开(公告)日：2023-07-27
申请号：US17826311
申请日：2022-05-27
Applicant: Qorvo US, Inc.
Inventor： Michael R. Kay , Nadim Khlat
CPC classification number: H03F3/245 , H03F1/565 , H03F1/0222 , H03F3/195 , H03F2200/451 , H03F2200/102
Abstract: Voltage ripple reduction in a power management circuit is disclosed. The power management circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage and an envelope tracking integrated circuit (ETIC) configured to provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, an output impedance presenting at an input of the power amplifier circuit can interact with a modulated load current in the power amplifier circuit to create a voltage ripple in the modulated voltage to potentially cause an undesirable error in the RF signal. Herein, the ETIC is configured to modify the modulated voltage based on feedback of the voltage ripple in the modulated voltage. As such, it is possible to reduce the output impedance at the input of the power amplifier circuit to thereby reduce the voltage ripple in the modulated voltage.
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公开(公告)号：US20220329217A1
公开(公告)日：2022-10-13
申请号：US17852857
申请日：2022-06-29
Applicant: Qorvo US, Inc.
Inventor： Nadim Khlat , Michael R. Kay , Michael J. Murphy
Abstract: A switch controller for charge pump tracker circuitry is disclosed. The switch controller includes first monitoring circuitry configured to monitor a first voltage across a first flying capacitor during a first discharging phase. A second monitoring circuitry is configured to monitor a second voltage across a second flying capacitor during a second discharging phase. Further included is boost logic circuitry in communication with the first monitoring circuitry and the second monitoring circuitry, wherein the boost logic circuitry is configured in response to control a first switch network coupled to the first flying capacitor and a second switch network coupled to the second flying capacitor so that the first discharging phase and the second discharging phase alternate in an interleaved mode, and so that the first discharging phase and the second discharging phase are in phase during a parallel boost mode.
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公开(公告)号：US11387789B2
公开(公告)日：2022-07-12
申请号：US16831935
申请日：2020-03-27
Applicant: Qorvo US, Inc.
Inventor： Nadim Khlat , Michael R. Kay , Michael J. Murphy
Abstract: Charge pump tracker circuitry is disclosed having a first switch network configured to couple a first flying capacitor between a voltage input terminal and a ground terminal during a first charging phase and couple the first flying capacitor between the voltage input terminal and a pump output terminal during a first discharging phase. A second switch network is configured to couple a second flying capacitor between the voltage input terminal and the ground terminal during a second charging phase and couple the second flying capacitor between the voltage input terminal and the pump output terminal during a second discharging phase. A switch controller is configured to monitor first and second voltages across the first and second flying capacitors, respectively, during the first and second discharging phases and in response to control the first and second switch networks so that the first the second discharging phases alternate in an interleaved mode.
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