-
41.发明申请公开(公告)号：US20200228376A1
公开(公告)日：2020-07-16
申请号：US16750924
申请日：2020-01-23
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
-
42.发明授权公开(公告)号：US10686632B2
公开(公告)日：2020-06-16
申请号：US16182724
申请日：2018-11-07
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
-
公开(公告)号：US20200052873A1
公开(公告)日：2020-02-13
申请号：US16549303
申请日：2019-08-23
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
-
公开(公告)号：US10536304B2
公开(公告)日：2020-01-14
申请号：US15670916
申请日：2017-08-07
Applicant: Rambus Inc.
Inventor： Qi Lin , Brian Leibowitz , Hae-Chang Lee , Jihong Ren , Kyung Suk Oh , Jared L. Zerbe
Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
-
公开(公告)号：US20180329859A1
公开(公告)日：2018-11-15
申请号：US15947701
申请日：2018-04-06
Applicant: Rambus Inc.
Inventor： Yohan U. Frans , Hae-Chang Lee , Brian S. Leibowitz , Simon Li , Nhat M. Nguyen
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02D50/10
Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
-
Patent Agency Ranking
46.发明申请公开(公告)号：US20180248718A1
公开(公告)日：2018-08-30
申请号：US15878149
申请日：2018-01-23
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
-
47.发明申请HIGH-SPEED SIGNALING SYSTEMS AND METHODS WITH ADAPTABLE, CONTINUOUS-TIME EQUALIZATION 有权高速信号系统和方法具有适应性，连续时间均衡公开(公告)号：US20170005839A1
公开(公告)日：2017-01-05
申请号：US15208332
申请日：2016-07-12
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
IPC: H04L25/03
CPC classification number: H04L25/03159 , H04B1/123 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
Abstract translation: 接收机包括连续时间均衡器，判决反馈均衡器（DFE），数据和误差采样逻辑以及适配引擎。 接收机通过基于第一后视标ISI的测量建立连续时间均衡器的适当均衡设置来校正与最新数据符号（第一后光标ISI）相关联的符号间干扰（ISI）。
-
公开(公告)号：US09419663B2
公开(公告)日：2016-08-16
申请号：US14552598
申请日：2014-11-25
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
CPC classification number: H04L25/03159 , H04B1/123 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
-
49.发明授权Clock and data recovery using receiver clock spread spectrum modulation and offset compensation 有权使用接收机时钟扩频调制和偏移补偿的时钟和数据恢复公开(公告)号：US09337992B2
公开(公告)日：2016-05-10
申请号：US14574253
申请日：2014-12-17
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
CPC classification number: H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.
Abstract translation: 一种用于执行时钟和数据恢复的系统和方法。 根据数据发送器时钟的频率和接收机时钟的频率之间的偏移的变化率的至少三个估计，系统设置恢复的时钟信号的相位。
-
50.发明申请METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 有权用于设备之间的通道均衡化的不对称分配的方法和电路公开(公告)号：US20150349986A1
公开(公告)日：2015-12-03
申请号：US14734426
申请日：2015-06-09
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。
-
-
-
-
-
-
-
-
-
Search Results
95
records
(took 0.019 seconds)
