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41.发明授权
公开(公告)号：US5777567A
公开(公告)日：1998-07-07
申请号：US663583
申请日：1996-06-14
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock lines typically found in other converters. The simplified circuit design also has the advantage of requiring minimal semiconductor layout area and reduced power requirements. One embodiment includes a buffer, a first data delay line, coupled to receive serial data from the buffer, and a phase lock loop (PLL), coupled to receive serial data from the buffer. A second data delay line is configured as a voltage controlled oscillator (VCO) within the PLL. The PLL locks onto the incoming serial data signal and provides a control signal back to the first data delay line to ensure it is storing serial data bits as they arrive. After n-bits of data have been transmitted the first data delay line contains a n-bit wide parallel word.
摘要翻译： 公开了一种串行数据到并行数据转换器，其具有在使用以较低频率工作的时钟信号的情况下将高频串行数据精确地转换为并行数据的优点。 通过避免使用通常在其他转换器中发现的多个高速时钟线来实现低误码率。 简化的电路设计还具有要求最小的半导体布局面积和降低的功率要求的优点。 一个实施例包括耦合以从缓冲器接收串行数据的缓冲器，第一数据延迟线和耦合以从缓冲器接收串行数据的锁相环（PLL）。 第二个数据延迟线被配置为PLL内的压控振荡器（VCO）。 PLL锁定到输入的串行数据信号上，并将控制信号提供回第一个数据延迟线，以确保它们到达时存储串行数据位。 在发送n位数据之后，第一数据延迟线包含n位宽的并行字。
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公开(公告)号：US4684826A
公开(公告)日：1987-08-04
申请号：US633164
申请日：1984-07-20
CPC分类号： H03K3/2865 , H03K3/289
摘要： A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.
摘要翻译： 根据本发明构造的电路包括响应于初始化输入信号（＆amp; upbar＆I）而将触发器（70）或寄存器异步强制到可编程逻辑状态的装置。 在一个实施例中，提供了一种D型触发器（70），具有数据输入端（71），时钟输入端（77），数据输出端（103），初始化输入端（41）和 编程输入端子（11）。 当接收到初始化输入信号＆upbar＆I时，预定义的输出信号立即被放置在数据输出端子（103）上。 预定义的输出信号由保险丝（13）的状态定义，熔丝（13）如果需要，通过编程输入端（11）打开。 当未接收到初始化输入信号时，触发器（70）作为正常D型触发器工作。
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公开(公告)号：US07333527B2
公开(公告)日：2008-02-19
申请号：US10306785
申请日：2002-11-27
CPC分类号： H04B15/04 , H04B2215/064 , H04B2215/067
摘要： The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The present invention seeks to reduce EMI emissions by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. In addition, the present invention is capable of generating a wide energy spectrum in a short time interval. Furthermore, the present invention can be similarly applied to other signals which exhibit a periodic or timing nature due to a correlation with the clock signal.
摘要翻译： 时钟信号是许多数字电子设备的电磁干扰（EMI）的主要来源。 必须抑制由这些电子设备产生的EMI，以避免与其他电子设备的干扰，并符合FCC规定。 本发明寻求通过使用可调延迟线对时钟信号进行相位调制来减少EMI发射。 相位调制导致时钟信号的能量谱的扩展，从而减少EMI辐射。 此外，本发明能够在短时间间隔内产生宽的能量谱。 此外，由于与时钟信号的相关性，本发明可以类似地应用于表现出周期性或定时性质的其他信号。
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44.发明授权Method and apparatus for detecting the position of light which is incident to a semiconductor die 有权用于检测入射到半导体管芯的光的位置的方法和装置公开(公告)号：US07217915B2
公开(公告)日：2007-05-15
申请号：US10840865
申请日：2004-05-07
申请人： Robert J. Bosnyak , Robert J. Drost
发明人： Robert J. Bosnyak , Robert J. Drost
CPC分类号： H04N5/335 , G01J1/44 , H01L27/14601
摘要： One embodiment of the present invention provides a system for detecting light which is incident to a first semiconductor die. During operation, the system receives light at a photo-detector on the first semiconductor die, wherein associated circuitry converts the received light into a current. In doing so, the associated circuitry biases a gate voltage of an integrating transistor to be close to a threshold voltage of the integrating transistor, and applies the current from the photo-detector to the gate of the integrating transistor so that the current causes a charge to collect at the gate of the integrating transistor. This charge builds up and causes the integrating transistor to switch, thereby indicating that light has been received by the photo-detector.
摘要翻译： 本发明的一个实施例提供了一种用于检测入射到第一半导体管芯的光的系统。 在操作期间，系统在第一半导体管芯上的光检测器处接收光，其中相关联的电路将接收的光转换成电流。 在这样做时，相关联的电路将积分晶体管的栅极电压偏置为接近积分晶体管的阈值电压，并将来自光电检测器的电流施加到积分晶体管的栅极，使得电流导致电荷 在积分晶体管的栅极处收集。 该电荷积聚并使积分晶体管切换，从而指示光已经被光电检测器接收。
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45.发明授权公开(公告)号：US06867629B2
公开(公告)日：2005-03-15
申请号：US10247401
申请日：2002-09-19
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
CPC分类号： H03K19/00 , H01L27/0808
摘要： The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block. In a particular embodiment, the method includes selecting a logic state of a digital input; applying the digital input to a parasitic capacitance block having an output, the output having a first capacitance when the digital input is in first logic state and a second capacitance when the digital input is in a second logic state; and adjusting a capacitance with respect to a second circuit node within the integrated circuit by applying the output to the second circuit node.
摘要翻译： 本发明涉及一种调整集成电路节点的电容的集成电路器件和方法。在一个实施例中，器件包括第一数字输入，第一寄生电容块，第一输出，第二数字输入，第二数字输入 寄生电容块和第二输出。 第一寄生电容块包括反相器，可变电容元件和线电容元件。 第一寄生电容块具有作为第一数字输入的函数的电容。 第一输出响应于第一寄生电容块，第二输出响应于第二寄生电容块。 在特定实施例中，该方法包括选择数字输入的逻辑状态; 将数字输入施加到具有输出的寄生电容块，当数字输入处于第一逻辑状态时，输出具有第一电容，当数字输入处于第二逻辑状态时具有第二电容; 以及通过将所述输出施加到所述第二电路节点来调整相对于所述集成电路内的第二电路节点的电容。
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公开(公告)号：US06600325B2
公开(公告)日：2003-07-29
申请号：US09778622
申请日：2001-02-06
IPC分类号： G01R3108
CPC分类号： G01R31/303 , G01R31/3025 , G01R31/312
摘要： One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.
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公开(公告)号：US06597593B1
公开(公告)日：2003-07-22
申请号：US09614664
申请日：2000-07-12
申请人： José M. Cruz , Robert J. Bosnyak , Shwetabh Verma
发明人： José M. Cruz , Robert J. Bosnyak , Shwetabh Verma
IPC分类号： H02M100
CPC分类号： H01L27/08 , G06F1/26 , H01F17/0006 , H01F19/04 , H01F27/2804 , H02M7/003
摘要： A power converter within an integrated circuit (“IC”) for providing DC power to one or more function circuit, where the power converter has a transformer circuit for receiving an AC power signal and for supplying a transformed AC power signal. A converter circuit receives the transformed AC power signal and then converts the signal into a DC power signal supplied to one or more function circuit. The transformed AC power signal might either be stepped up or stepped down. The transformer circuit might comprise two coils, where a first coil is magnetically coupled to a second coil. The first coil is a first spiral and the second coil is a second spiral wherein an insulating material layer is disposed between the first spiral and the second spiral. The transformer circuit might include transformers connected in parallel or in series and may further be connected correspondingly to more than one converter circuit coupled in parallel. An IC comprising the power converter circuit can be integrated into a computer system.
摘要翻译： 用于向一个或多个功能电路提供直流电力的集成电路（“IC”）内的功率转换器，其中功率转换器具有用于接收AC电力信号的变压器电路并用于提供经变换的AC电力信号。 A转换器电路接收经变换的AC电力信号，然后将该信号转换为提供给一个或多个功能电路的直流电力信号。 变换后的交流电源信号可能会升高或降低。 变压器电路可以包括两个线圈，其中第一线圈磁耦合到第二线圈。 第一线圈是第一螺旋，第二线圈是第二螺旋形，其中绝缘材料层设置在第一螺旋和第二螺旋之间。 变压器电路可以包括并联或串联连接的变压器，并且可以进一步相应地连接到并联耦合的多于一个的转换器电路。 包括电源转换器电路的IC可以集成到计算机系统中。
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公开(公告)号：US06515501B2
公开(公告)日：2003-02-04
申请号：US09873093
申请日：2001-06-01
IPC分类号： H03K19003
CPC分类号： H05K1/025 , H05K1/181 , H05K3/222 , H05K2201/09236 , H05K2201/10212 , H05K2201/10689
摘要： An improved signal buffer configuration has been developed for transmitting communication signals across line traces between ICs on a printed circuit board, printed wiring board, multi-chip module, integrated circuit carrier or package, or other interconnect substrate. For example, in some realizations, multiple ICs having mismatched input and output impedances are mounted on an printed circuit board and communicate with each other via line traces. A signal buffer IC is placed in-line with the connecting line trace. The buffer is sized to fit within the pitch spacing of the line trace and contains an input impedance control circuit and an output impedance control circuit. These impedance control circuits are adapted to receive a control signal to set the input and output impedances of the buffer to correspond to the impedances of the connecting line traces. In this manner, the impedances between the ICs connected by this line trace are effectively matched and transmission line errors between them are reduced.
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49.发明授权公开(公告)号：US06362678B1
公开(公告)日：2002-03-26
申请号：US09468710
申请日：1999-12-21
申请人： Robert J. Bosnyak , José M. Cruz
发明人： Robert J. Bosnyak , José M. Cruz
IPC分类号： H03K1704
CPC分类号： H03K19/0136 , H03K19/01728
摘要： An improved output driver for HSTL includes a bias control transistor to absorb current leaking through the base-collector capacitance of the drive transistor and maintain the base voltage on the drive transistor. The bias control transistor is biased by a series network coupled between a base of the bias control transistor and ground, which keeps the bias control transistor at a bias near its turn-on bias, with a feedback capacitor coupled between the output and the base of the bias control transistor to turn on the bias control transistor when the output rises.
摘要翻译： 用于HSTL的改进的输出驱动器包括偏置控制晶体管，以吸收通过驱动晶体管的基极 - 集电极电容泄漏的电流并且维持驱动晶体管上的基极电压。 偏置控制晶体管被耦合在偏置控制晶体管的基极和接地之间的串联网络偏置，该偏置控制晶体管的基极与接地之间保持偏置控制晶体管的偏压，反馈电容器耦合在输出和基极之间 偏置控制晶体管，当输出上升时导通偏置控制晶体管。
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公开(公告)号：US06329836B1
公开(公告)日：2001-12-11
申请号：US09580312
申请日：2000-05-26
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
IPC分类号： H03K1716
CPC分类号： H03K17/167 , H03K5/01 , H03K17/164 , H03K19/00361 , H04L25/03834
摘要： A high speed self-terminated output driver includes an array of resistive drivers that are pulse-activated in succession to process a corresponding succession of data bits. The output driver thus synthesizes an output waveform which behaves similar to a single resistive drive element responding to the non-bandlimited input signal. In various embodiment, the output driver provides for digitally programmable output impedance and pre-distortion levels.
摘要翻译： 高速自终端输出驱动器包括电阻驱动器阵列，其被连续地脉冲激活以处理对应的一系列数据位。 因此，输出驱动器合成响应于非带限输入信号的类似于单个电阻驱动元件的输出波形。 在各种实施例中，输出驱动器提供数字可编程输出阻抗和预失真电平。
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