公开(公告)号：US09236380B2

公开(公告)日：2016-01-12

申请号：US14050576

申请日：2013-10-10

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上半导体（SOI）晶片的第一半导体层上形成第二半导体层，该第二半导体层包括与第一半导体层的第一半导体材料不同的第二半导体材料。 该方法还可以包括在非氧化性气氛中进行热处理，以将第二半导体材料扩散到第一半导体层中，以及去除第二半导体层。

公开(公告)号：US09224845B1

公开(公告)日：2015-12-29

申请号：US14538877

申请日：2014-11-12

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Pierre Morin

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/772 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L21/04 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L29/7722 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/308 ,  H01L27/0225 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66416

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

Abstract translation: 在掺杂有第一导电类型的碳化硅衬底上形成静电感应晶体管。 在碳化硅衬底的顶表面中的第一凹陷区域填充有原位掺杂有第二导电类型的外延生长栅极区域。 原位掺杂有第一导电类型的外延生长沟道区位于相邻的外延栅区之间。 原位掺杂有第一导电类型的外延生长的源极区位于外延沟道区上。 碳化硅衬底的底表面包括与沟道区垂直对准的第二凹陷区域并硅​​化以支持漏极接触的形成。 源区的顶表面被硅化以支持源接触的形成。 栅极引线外延生长并电耦合到栅极区域，栅极引线硅化以支持栅极接触的形成。

公开(公告)号：US20140357040A1

公开(公告)日：2014-12-04

申请号：US13905586

申请日：2013-05-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Abstract translation: 制造半导体器件的方法包括在第一半导体材料层上形成用于至少一个栅极叠层的第一间隔物，以及与邻近所述至少一个栅极的每个源区和漏区形成相应的第二间隔物。 每个第二间隔件具有一对相对的侧壁和与其连接的端壁。 该方法包括用第二半导体材料填充源区和漏区，而第一和第二间隔件提供约束。

公开(公告)号：US11264286B2

公开(公告)日：2022-03-01

申请号：US16445778

申请日：2019-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US10600786B2

公开(公告)日：2020-03-24

申请号：US15452049

申请日：2017-03-07

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Sylvain Maitrejean ,  Emmanuel Augendre ,  Pierre Morin ,  Shay Reboh

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/266 ,  H01L21/268 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

公开(公告)号：US20190189802A1

公开(公告)日：2019-06-20

申请号：US16212632

申请日：2018-12-06

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10204982B2

公开(公告)日：2019-02-12

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

公开(公告)号：US10177255B2

公开(公告)日：2019-01-08

申请号：US15723152

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US20180331106A1

公开(公告)日：2018-11-15

申请号：US16035441

申请日：2018-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US10043805B2

公开(公告)日：2018-08-07

申请号：US15197509

申请日：2016-06-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.