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    FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
    41.
    发明申请
    FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION 有权
    FINFET集成电路及其制造方法

    公开(公告)号：US20150179644A1

    公开(公告)日：2015-06-25

    申请号：US14615762

    申请日：2015-02-06

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

    IPC: H01L27/088 ,  H01L29/06

    CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

    Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

    Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

    Grating couplers with cladding layer(s)
    45.
    发明授权
    Grating couplers with cladding layer(s) 有权

    公开(公告)号：US10746907B2

    公开(公告)日：2020-08-18

    申请号：US15945347

    申请日：2018-04-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian

    IPC: G02B5/18 ,  G02B6/30 ,  G02B6/34

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with structured cladding and methods of manufacture. A structure includes: a grating coupler in a dielectric material; a back end of line (BEOL) multilayer stack over the dielectric material; and a multi-layered cladding structure of alternating materials directly on the BEOL multilayer stack.

    Electro-optic modulators with layered arrangements
    46.
    发明授权
    Electro-optic modulators with layered arrangements 有权

    公开(公告)号：US10684530B1

    公开(公告)日：2020-06-16

    申请号：US16288634

    申请日：2019-02-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Abu Thomas

    IPC: G02F1/29

    Abstract: Structures for an electro-optic modulator and methods of fabricating a structure for an electro-optic modulator. An electro-optic modulator is arranged over a portion of a waveguide core. The electro-optic modulator includes an electrode, an active layer arranged adjacent to the electrode, and a dielectric layer including a portion that has a lateral arrangement between the electrode and the active layer. The active layer is composed of a material having a refractive index that is a function of a bias voltage applied to the electrode and the active layer.

    Integrated circuits including magnetic random access memory structures and methods for fabricating the same
    48.
    发明授权
    Integrated circuits including magnetic random access memory structures and methods for fabricating the same 有权

    公开(公告)号：US10411069B1

    公开(公告)日：2019-09-10

    申请号：US15898547

    申请日：2018-02-17

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.

    INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME
    49.
    发明申请
    INTEGRATED CIRCUITS INCLUDING MAGNETIC RANDOM ACCESS MEMORY STRUCTURES AND METHODS FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190259808A1

    公开(公告)日：2019-08-22

    申请号：US15898547

    申请日：2018-02-17

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.

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