公开(公告)号：US10910428B2

公开(公告)日：2021-02-02

申请号：US16212790

申请日：2018-12-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Sonarith Chhun

IPC: H01L27/146

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US10566376B2

公开(公告)日：2020-02-18

申请号：US16112241

申请日：2018-08-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Frédéric Lalanne ,  Pierre Emmanuel Marie Malinge

IPC: H01L27/146 ,  H04N5/378

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

公开(公告)号：US10535693B2

公开(公告)日：2020-01-14

申请号：US15916912

申请日：2018-03-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.

公开(公告)号：US10531022B2

公开(公告)日：2020-01-07

申请号：US15995249

申请日：2018-06-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H04N5/353 ,  H01L27/146 ,  H04N5/372 ,  H04N5/378 ,  H04N5/363

Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

公开(公告)号：US10475848B2

公开(公告)日：2019-11-12

申请号：US15839011

申请日：2017-12-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/148 ,  H01L27/146 ,  H04N9/00

Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.

公开(公告)号：US20190086519A1

公开(公告)日：2019-03-21

申请号：US16194985

申请日：2018-11-19

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Boris Rodrigues Goncalves ,  Marie Guillon ,  Yvon Cazaux ,  Benoit Giffard

IPC: G01S7/486 ,  H01L27/146 ,  G01S7/491 ,  H04N5/374

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

公开(公告)号：US20180012926A1

公开(公告)日：2018-01-11

申请号：US15703246

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14689

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US20160351611A1

公开(公告)日：2016-12-01

申请号：US14959687

申请日：2015-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/1464 ,  H01L27/14685

Abstract: A back-side imager includes a matrix of photosites in an active layer. An interconnect layer covers the active layer. A layer of germanium is positioned between the active layer and the interconnect layer.

Abstract translation: 背面成像器包括有源层中的光子矩阵。 互连层覆盖有源层。 锗层位于有源层和互连层之间。

公开(公告)号：US12040335B2

公开(公告)日：2024-07-16

申请号：US17944529

申请日：2022-09-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146 ,  H04N25/53 ,  H04N25/621 ,  H04N25/705 ,  H04N25/75 ,  H04N25/77

CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H04N25/53 ,  H04N25/621 ,  H04N25/705 ,  H04N25/75 ,  H04N25/77

Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.

公开(公告)号：US11695028B2

公开(公告)日：2023-07-04

申请号：US17514953

申请日：2021-10-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Stephane Hulot ,  Andrej Suler ,  Nicolas Virollet

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14621 ,  H01L27/14627

Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.