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公开(公告)号：US20190028024A1
公开(公告)日：2019-01-24
申请号：US15652447
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
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公开(公告)号：US09755632B2
公开(公告)日：2017-09-05
申请号：US14826017
申请日：2015-08-13
Inventor： Vikas Rana , Fabio De Santis
CPC classification number: H03K17/102
Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
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公开(公告)号：US09659933B2
公开(公告)日：2017-05-23
申请号：US14697461
申请日：2015-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Amit Chhabra
IPC: H03K17/693 , H01L27/092 , H01L27/12 , H03K17/00
CPC classification number: H03K17/693 , H01L27/092 , H01L27/1203 , H03K17/005 , H03K2217/0018
Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.
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公开(公告)号：US20160099033A1
公开(公告)日：2016-04-07
申请号：US14506865
申请日：2014-10-06
Inventor： Abhishek Lal , Vikas Rana , Marco Pasotti
Abstract: A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.
Abstract translation: 存储器包括列解码器，其使用在列位线和第一电平解码线之间解码的第一电平解码器和在第一电平解码线和第二电平解码线之间解码的第二电平解码器来执行解码的至少两个级别。 第二电平解码器包括耦合在第一电平解码线和读出输出线之间的第一晶体管和耦合在第一电平解码线和写输入线之间的第二晶体管。 第一晶体管具有第一电压额定值，并且由与第一额定电压兼容的低电源电压参考的解码控制信号驱动。 第二晶体管具有高于第一电压额定值的第二电压额定值，并且由与第二额定电压兼容的高电源电压（超过低电源电压）的解码控制信号驱动。
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45.发明授权Non-volatile memory with reduced sub-threshold leakage during program and erase operations 有权在编程和擦除操作期间具有减少的亚阈值泄漏的非易失性存储器公开(公告)号：US09159425B2
公开(公告)日：2015-10-13
申请号：US14089016
申请日：2013-11-25
Inventor： Vikas Rana , Ganesh Raj R , Fabio De Santis
CPC classification number: G11C16/0433
Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.
Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。
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Patent Agency Ranking
46.发明申请NON-VOLATILE MEMORY WITH REDUCED SUB-THRESHOLD LEAKAGE DURING PROGRAM AND ERASE OPERATIONS 有权在程序和擦除操作期间具有降低的次级阈值漏电的非易失性存储器公开(公告)号：US20150146490A1
公开(公告)日：2015-05-28
申请号：US14089016
申请日：2013-11-25
Inventor： Vikas Rana , Ganesh Raj R , Fabio De Santis
IPC: G11C16/14
CPC classification number: G11C16/0433
Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.
Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。
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公开(公告)号：US12094542B2
公开(公告)日：2024-09-17
申请号：US17542323
申请日：2021-12-03
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Neha Dalal
CPC classification number: G11C16/26 , G11C16/0408 , G11C16/08 , G11C16/30 , G11C16/32
Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.
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公开(公告)号：US11764673B2
公开(公告)日：2023-09-19
申请号：US17673033
申请日：2022-02-16
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07
CPC classification number: H02M3/071
Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.
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公开(公告)号：US11615820B1
公开(公告)日：2023-03-28
申请号：US17490976
申请日：2021-09-30
Inventor： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US11424676B2
公开(公告)日：2022-08-23
申请号：US17145107
申请日：2021-01-08
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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