公开(公告)号：US09875791B2

公开(公告)日：2018-01-23

申请号：US15664591

申请日：2017-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jin Kwon ,  Kang-Ill Seo

IPC: H01L27/11 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is connected to the first channel pattern.

公开(公告)号：US09806194B2

公开(公告)日：2017-10-31

申请号：US14800054

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a second fin area. A gate structure is disposed on the first fin area. A source region is in contact with the second fin area. The first fin area includes the first material at a first concentration, the second fin area includes the first material at a second concentration which is greater than the first concentration.

公开(公告)号：US09716041B2

公开(公告)日：2017-07-25

申请号：US14751594

申请日：2015-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Kang-Ill Seo

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/417 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating a semiconductor device includes forming a pre-fin extending in a first direction, the pre-fin including first, second, and third regions, forming first and second gates on the pre-fin to extend in a second direction intersecting the first direction, the first and second gates being spaced apart from each other in the first direction and overlapping with the first and second regions, respectively, forming first and second dummy spacers on the first and second regions, respectively to form a first trench in the third region that exposes the third region, forming a second trench by etching the exposed third region using the first and second dummy spacers as masks to separate the pre-fin into first and second active fins corresponding to the first and second regions, respectively, forming a dummy gate by filling the first and second trenches and removing the first and second dummy spacers.

公开(公告)号：US09653361B2

公开(公告)日：2017-05-16

申请号：US15199502

申请日：2016-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il Bae ,  Kang-Ill Seo

IPC: H01L27/12 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern disposed on the sacrificial layer pattern, and a gate dielectric layer and a gate electrode layer extending through the sacrificial layer pattern and surrounding a portion of the active layer pattern.

公开(公告)号：US09472653B2

公开(公告)日：2016-10-18

申请号：US14554107

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyuk Kim ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成多个目标图案。 多个目标图案沿着第一方向彼此平行地延伸。 形成在第一方向上延伸并且包括多个第一开口的第一掩模图案。 形成沿与第一方向交叉的第二方向延伸并且包括多个第二开口的第二掩模图案。 每个第二开口与每个第一开口重叠以形成重叠的开口区域。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，通过重叠的开口区域蚀刻多个目标图案的区域。 多个目标图案的区域与重叠的开口区域重叠。

公开(公告)号：US09362311B1

公开(公告)日：2016-06-07

申请号：US14808027

申请日：2015-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02664 ,  H01L21/02694 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device is provided. A first semiconductor layer including Ge at a first concentration is formed on an insulation layer. Second and third semiconductor layers are formed sequentially on the first semiconductor layer. The second and third semiconductor layers include Ge at second and third concentrations higher than the first concentration. A fin type structure is formed by patterning the insulation layer and the first to third semiconductor layers. The fin type structure is vertically protruded. A fin type active pattern is formed on the fin type structure by performing a first thermal process on the fin type structure. The fin type active pattern includes Ge at a fourth concentration higher than the first concentration and lower than the second concentration.

Abstract translation: 提供一种制造半导体器件的方法。 包含第一浓度的Ge的第一半导体层形成在绝缘层上。 在第一半导体层上依次形成第二和第三半导体层。 第二和第三半导体层包括高于第一浓度的第二和第三浓度的Ge。 通过图案化绝缘层和第一至第三半导体层来形成鳍型结构。 鳍型结构垂直突出。 通过对翅片型结构进行第一热处理，在翅片型结构上形成翅片型有源图案。 翅片型有源图案包括比第一浓度高于第二浓度的第四浓度的Ge。

公开(公告)号：US09343370B1

公开(公告)日：2016-05-17

申请号：US14555775

申请日：2014-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Seok Lee ,  Kang-Ill Seo

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/845 ,  H01L29/66795

Abstract: An exemplary method of fabricating a semiconductor device is provided. First and second hard mask patterns adjacent to each other are formed on a substrate. First and second active fins are formed by etching the substrate using the first and second hard mask patterns as a etch mask. An isolation layer is formed to fill a region defined by the first and second active fins and the first and second hard mask patterns. A mask pattern is formed to be positioned on the first hard mask pattern and overlap the first active fin. A first trench is formed by etching a portion of the isolation layer and a portion of the second active fin using the mask pattern as an etch mask. The remaining portion of the second active fin is removed by performing an isotropic etching process.

Abstract translation: 提供了一种制造半导体器件的示例性方法。 在基板上形成彼此相邻的第一和第二硬掩模图案。 通过使用第一和第二硬掩模图案作为蚀刻掩模蚀刻衬底来形成第一和第二活性鳍。 形成隔离层以填充由第一和第二活动鳍片以及第一和第二硬掩模图案限定的区域。 形成掩模图案以定位在第一硬掩模图案上并且与第一活动散热片重叠。 通过使用掩模图案作为蚀刻掩模蚀刻隔离层的一部分和第二有源散热片的一部分来形成第一沟槽。 通过执行各向同性蚀刻工艺来去除第二活性鳍片的剩余部分。